Through silicon via with dummy structure and method for forming the same

• US 7,969,013 B2
• Filed: 06/02/2010
• Issued: 06/28/2011
• Est. Priority Date: 10/22/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Chen-Cheng, Shen, Wen-Wei, Chen, Chih-Hua, Chen, Chen-Shien
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): Payen; Marvin
• Application Number:
  US12/791,978
• Publication Number:
  US 20110095436A1
• Time in Patent Office: 391 Days
• Field of Search: 257/773, 257/774, 257/E23.07, 257/E23.174, 438/621, 438637-640
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A through silicon via structure includes a top pad and a vertical conductive post that is connected to the top pad. The top pad covers a wider area than the cross section of the vertical conductive post. An interconnect pad is formed at least partially below the top pad. An under layer is also formed at least partially below the top pad. At least one dummy structure connects the top pad and the under layer to fasten the top pad and the interconnect pad.

Claims

1. A through silicon via (TSV) structure, comprising:

a top pad;

a vertical conductive post connected to the top pad, wherein the top pad covers a wider area than a cross section of the vertical conductive post;

an interconnect pad connected to the top pad and at least partially below the top pad;

an under layer at least partially below the top pad; and

at least one dummy structure connecting the top pad and the under layer to fasten the top pad and the interconnect pad.

2. The TSV structure of claim 1, comprising a plurality of said dummy structures distributed around the vertical conductive post.

3. The TSV structure of claim 2, wherein the dummy structures are distributed uniformly under the top pad except in an area where the top pad is connected to the vertical conductive post.

4. The TSV structure of claim 2, wherein the dummy structures are distributed in a square grid pattern.

5. The TSV structure of claim 2, wherein the dummy structures are distributed in a circular pattern around the vertical conductive post.

6. The TSV structure of claim 1, comprising a plurality of said dummy structures having a linear shape.

7. The TSV structure of claim 6, wherein the linear shape is a straight line.

8. The TSV structure of claim 6, wherein the dummy structures are evenly spaced from each other.

9. The TSV structure of claim 6, wherein the dummy structures have at least two different lengths.

10. An integrated circuit having a through silicon via structure, comprising:

a substrate;

a top pad over the substrate;

a vertical conductive post connected to the top pad and at least partially through the substrate, wherein the top pad covers a wider area than a cross section of the vertical conductive post;

an interconnect pad connected to the top pad and at least partially below the top pad;

an under layer at least partially below the top pad; and

at least one dummy structure connecting the top pad and the under layer to fasten the top pad and the interconnect pad.