Differential sensing and TSV timing control scheme for 3D-IC
First Claim
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1. A differential sensing and TSV timing control scheme for a stacked device having pluralities chip layers, comprising:
- a first chip layer of said stacked device including a timing-detecting circuit and a relative high ability driver at the same chip layer horizontally coupled to said timing-detecting circuit;
a sensing circuit coupled to said timing-detecting circuit in said first chip layer by a horizontal conductive line;
a first differential signal driver coupled to said sensing circuit horizontally in said first chip layer;
a Nth chip layer of said stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on said Nth chip layer;
wherein said N is a nature number and is more than one;
wherein said Nth relative high ability driver is vertically coupled to said first relative high ability driver through one relative low loading TSV and (N−
2) relative high loading TSVs to act dummy loadings, said relative low loading TSV and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer, wherein said relative low loading TSV and said (N−
2) relative high loading TSVs are formed in a shared configuration;
wherein said Nth differential signal driver is vertically coupled to said first differential signal driver through a pair of relative low loading TSVs and (N−
2) pairs of relative high loading TSVs, vertically, said pair of relative low loading TSVs and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer; and
each said relative low loading TSV being formed between said first and a second chip layers, each said relative high loading TSV being formed between any adjacent two chip layers of said stacked device;
whereby said detecting circuit activates said sensing circuit when an active signal reaches to a trigger point.
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Abstract
This disclosure uses a differential sensing and TSV timing control scheme for 3D-IC, which includes a first chip layer of the stacked device having a detecting circuits and a relative high ability driver horizontally coupled to the detecting circuits. A sensing circuit is coupled to the detecting circuits by a horizontal line, a first differential signal driver is coupled to the sensing circuit, horizontally. The Nth chip layer of the stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on the Nth chip layer. The Nth relative high ability driver is vertically coupled to the first relative high ability driver through one relative low loading TSV and (N−2) TSVs to act as dummy loadings. The TSV and (N−2) TSVs penetrate the stacked device from Nth chip layer to first chip layer. The TSV shares same configuration with the (N−2) TSVs. The Nth differential signal driver is vertically coupled to the first differential signal driver through a pair of TSVs and (N−2) pairs of TSVs, vertically. The pair of TSVs and the (N−2) TSVs penetrate the stacked device from the Nth chip layer to the first chip layer. Each of TSV is formed between a first and a second chip layers. Each of TSV is formed between any adjacent two chip layers of the stacked device.
202 Citations
20 Claims
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1. A differential sensing and TSV timing control scheme for a stacked device having pluralities chip layers, comprising:
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a first chip layer of said stacked device including a timing-detecting circuit and a relative high ability driver at the same chip layer horizontally coupled to said timing-detecting circuit; a sensing circuit coupled to said timing-detecting circuit in said first chip layer by a horizontal conductive line; a first differential signal driver coupled to said sensing circuit horizontally in said first chip layer; a Nth chip layer of said stacked device includes a Nth relative high ability driver and a Nth differential signal driver formed on said Nth chip layer;
wherein said N is a nature number and is more than one;
wherein said Nth relative high ability driver is vertically coupled to said first relative high ability driver through one relative low loading TSV and (N−
2) relative high loading TSVs to act dummy loadings, said relative low loading TSV and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer, wherein said relative low loading TSV and said (N−
2) relative high loading TSVs are formed in a shared configuration;
wherein said Nth differential signal driver is vertically coupled to said first differential signal driver through a pair of relative low loading TSVs and (N−
2) pairs of relative high loading TSVs, vertically, said pair of relative low loading TSVs and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer; and
each said relative low loading TSV being formed between said first and a second chip layers, each said relative high loading TSV being formed between any adjacent two chip layers of said stacked device;
whereby said detecting circuit activates said sensing circuit when an active signal reaches to a trigger point. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A differential sensing and TSV timing control scheme for a stacked device having pluralities chip layers, comprising:
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a first chip layer of said stacked device including a detecting circuits and a relative high ability buffer horizontally coupled to said detecting circuits; a sensing circuit coupled to said detecting circuits by a horizontal conductive line; a first differential signal buffer coupled to said sensing circuit, horizontally; a Nth chip layer of said stacked device includes a Nth relative high ability buffer and a Nth differential signal buffer formed on said Nth chip layer;
wherein said N is a nature number and is more than one;
wherein said Nth relative high ability buffer is vertically coupled to said first relative high ability buffer through one relative low loading TSV and (N−
2) relative high loading TSVs to act dummy loadings, said relative low loading TSV and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer, wherein said relative low loading TSV and said (N−
2) relative high loading TSVs are formed in a shared configuration;
wherein said Nth differential signal buffer is vertically coupled to said first differential signal buffer through a pair of relative low loading TSVs and (N−
2) pairs of relative high loading TSVs, vertically, said pair of relative low loading TSVs and said (N−
2) relative high loading TSVs penetrating said stacked device from said Nth chip layer to said first chip layer; and
each said relative low loading TSV being formed between said first and a second chip layers, each said relative high loading TSV being formed between any adjacent two chip layers of said stacked device;
whereby said detecting circuit activates said sensing circuit when an active signal reaches to a trigger point. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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Current AssigneeNational Tsing Hua University
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Original AssigneeNational Tsing Hua University
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InventorsWu, Wei-Cheng, Chang, Meng-Fan, Chen, Yen-Huei
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Primary Examiner(s)CRAWFORD, JASON
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Application NumberUS12/830,469Time in Patent Office357 DaysField of Search326/37, 326/41, 326/47, 326/82, 257/758, 257/777, 716118-119, 716/126US Class Current326/82CPC Class CodesH01L 2225/06541 Conductive via connections ...H01L 25/0657 Stacked arrangements of dev...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...H03K 19/0175 Coupling arrangements; Inte...
