Method to improve inductance with a high-permeability slotted plate core in an integrated circuit

• US 7,969,274 B2
• Filed: 09/02/2008
• Issued: 06/28/2011
• Est. Priority Date: 07/30/2004
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Brennan, Kenneth D., Williams, Byron, Papa Rao, Satyavolu S.
• Primary Examiner(s): Mai; Anh
• Assistant Examiner(s): BAISA, JOSELITO SASIS
• Application Number:
  US12/202,665
• Publication Number:
  US 20090002115A1
• Time in Patent Office: 1,029 Days
• Field of Search: 336/200, 336/223, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 2017/008 Electric or magnetic shielding of printed inductances
• CPC Class Codes: H01F 41/046 structurally combined with ferromagnetic material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/49073 by assembling coil and core

Abstract

An inductor structure (102) formed in an integrated circuit (100) is disclosed, and includes a first isolation layer (106) and a first core plate (104) disposed over or within the first isolation layer (106, 114). The first core plate (104) includes a plurality of electrically coupled conductive traces composed of a conductive ferromagnetic material layer. A second isolation layer (108) overlies the first isolation layer and an inductor coil (102) composed of a conductive material layer (118) is formed within the second isolation layer (108). Another core plate may be formed over the coil. The one or more core plates increase an inductance (L) of the inductor coil (102).

Claims

1. An inductor structure formed in an integrated circuit, comprising:

a first isolation layer;

a conductive material layer located over the first isolation layer, and defining an inductor coil with laterally spaced multiple turns;

a core plate layer comprising a conductive ferromagnetic material conformally located overlying and extending between adjacent ones of the inductor coil turns; and

a second isolation layer conformally formed over the conductive material layer, between the conductive material layer and the core plate layer.

2. The method of claim 1, wherein the core plate is patterned with slots to avoid eddy currents.

3. The method of claim 1, wherein the core plate is patterned with a configuration having a plurality of conductive traces separated by spaces, and a web electrically connecting the conductive traces.

4. A semiconductor device, comprising:

a semiconductor substrate;

a metal interconnect layer formed in the substrate;

a dielectric layer formed overlying the metal interconnect layer;

a conductive via formed within the dielectric layer connecting to the metal interconnect layer;

at least one protective overcoat layer formed over the dielectric layer;

a conductive material layer formed within openings in the at least one protective overcoat layer and defining an inductor coil having laterally spaced multiple turns with an end terminal connecting to the conductive via;

an insulation layer disposed conformally overlying and extending between the inductor coil turns; and

a conductive ferromagnetic material layer disposed conformally overlying and extending between the inductor turns over the insulation layer.

5. The device of claim 4, wherein the at least one protective layer comprises first and second protective overcoat layers;

the first protective overcoat layer is formed over the dielectric layer;

the conductive material layer is formed over the first protective overcoat layer; and

the second protective overcoat layer is formed over the conductive material layer.

6. The device of claim 5, further comprising a first etch stop layer formed between the metal interconnect layer and the dielectric layer;

and a second etch stop layer formed between the dielectric layer and the at least one protective overcoat layer.

7. The device of claim 6, wherein the conductive material layer comprises copper, aluminum or a TaN/Al stack.

8. The device of claim 7, wherein the conductive ferromagnetic material layer comprises cobalt, nickel, tantalum, a TiN/Co/TiN stack or a TaN/Co stack.

9. A method of forming an integrated inductor structure over a semiconductor substrate, comprising:

providing a first isolation layer disposed over the semiconductor substrate;

forming and patterning a conductive material layer to define an inductor coil having laterally spaced multiple turns and overlying the first isolation layer;

forming a second isolation layer conformally over the inductor coil;

forming a core plate comprising a conductive ferromagnetic material conformally overlying the second isolation layer, overlying and extending between adjacent ones of the inductor coil turns; and

forming a third isolation layer over the core plate.

10. The method of claim 9, wherein the core plate of the inductor further comprises a capacitor plate, and wherein the plate of the capacitor is electrically connected to the inductor coil.

11. The method of claim 9, wherein the core plate is patterned with slots to avoid eddy currents.

12. The method of claim 9, wherein the core plate is patterned with a configuration having a plurality of conductive traces separated by spaces, and a web electrically connecting the conductive traces.