Device having power generating black mask and method of fabricating the same

• US 7,969,641 B2
• Filed: 02/13/2009
• Issued: 06/28/2011
• Est. Priority Date: 02/14/2008
• Status: Expired due to Fees

• Current Assignee: Snaptrack Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm MEMS Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Xu, Gang, Bita, Ion, Wang, Chun-Ming
• Primary Examiner(s): Thompson; Timothy J
• Application Number:
  US12/371,538
• Publication Number:
  US 20090207473A1
• Time in Patent Office: 865 Days
• Field of Search: 359/290, 359/315, 359/242, 359/245, 349/27, 349/149
• US Class Current: 359/290
• CPC Class Codes: G02B 26/001 based on interference in an adjustable optical cavity interference filters G02B5/28; devices or arrangements using multiple reflections in spectrometry or monochromators G01J3/26
• CPC Class Codes: G02F 1/13324 Circuits comprising solar cells
• CPC Class Codes: G02F 1/133512 Light shielding layers, e.g. black matrix G02F1/136209 takes precedence
• CPC Class Codes: Y02E 10/52 PV systems with concentrators

Abstract

A power generating black mask comprising an anti-reflection layer deposited over a substrate, a first electrode layer deposited over the anti-reflection layer, a semi-conductor layer deposited over the first electrode layer and a second electrode layer deposited over the semi-conductor layer.

Claims

1. An electronic device comprising:

a display area comprising a plurality of optical display elements, and

a photovoltaic black mask deposited in the areas between the optical display elements of the display area and positioned between a substrate and the optical display elements, wherein the photovoltaic black mask comprises;

at least one layer being configured to absorb light,

at least one layer being configured to generate power,

an anti-reflection layer deposited over a substrate,

a first electrode layer deposited over the anti-reflection layer,

a semiconductor layer deposited over the first electrode layer, and

a second electrode layer deposited over the semiconductor layer,

wherein the anti-reflection layer comprises at least one layer of material.

2. The electronic device of claim 1, wherein the photovoltaic black mask comprises at least ten percent of the display area.

3. An electronic device comprising:

a display area comprising a plurality of optical display elements, and

a photovoltaic black mask deposited in the areas between the optical display elements of the display area and positioned between a substrate and the optical display elements, wherein the photovoltaic black mask comprises;

at least one layer being configured to absorb light,

at least one layer being configured to generate power,

an anti-reflection layer deposited over a substrate,

a first electrode layer deposited over the anti-reflection layer,

a semiconductor layer deposited over the first electrode layer, and

a second electrode layer deposited over the semiconductor layer,

wherein the photovoltaic black mask is patterned such that an opening is formed through the second electrode layer and the semiconductor layer to the first electrode layer,

wherein an insulator is positioned over the second electrode layer and semiconductor layers, and

wherein the insulator is patterned such that an opening is formed through the insulator to the second first electrode layer.

4. An electronic device comprising:

a display area comprising a plurality of optical display elements, and

a photovoltaic black mask deposited in the areas between the optical display elements of the display area and positioned between a substrate and the optical display elements, wherein the photovoltaic black mask comprises;

at least one layer being configured to absorb light,

at least one layer being configured to generate power,

an anti-reflection layer deposited over a substrate,

a first electrode layer deposited over the anti-reflection layer,

a semiconductor layer deposited over the first electrode layer, and

a second electrode layer deposited over the semiconductor layer,

wherein an insulator is positioned over the second electrode layer, and

wherein the photovoltaic black mask is patterned such that an opening is formed through the insulator to the second electrode layer.

5. An electronic device comprising:

a display area comprising a plurality of optical display elements, and

a photovoltaic black mask deposited in the areas between the optical display elements of the display area and positioned between a substrate and the optical display elements, wherein the photovoltaic black mask comprises;

at least one layer being configured to absorb light,

at least one layer being configured to generate power,

an anti-reflection layer deposited over a substrate,

a first electrode layer deposited over the anti-reflection layer,

a semiconductor layer deposited over the first electrode layer, and

a second electrode layer deposited over the semiconductor layer,

wherein the photovoltaic black mask is patterned into discrete sections.

6. The electronic device of claim 5, wherein the electrodes in the sections are connected in series or in parallel.

7. A method of making a photovoltaic black mask, the method comprising:

depositing an anti-reflection layer over a substrate;

depositing a first electrode over the anti-reflection layer;

depositing a semiconductor layer over the first electrode layer;

depositing a second electrode over the semiconductor layer; and

patterning a portion of the anti-reflection layer, the first electrode layer, the semiconductor layer, and the second electrode layer.

8. The method of claim 7, wherein the anti-reflection layer comprises at least one layer of material.

9. The method of claim 7, the method further comprising depositing a planarization layer over a portion of the first electrode layer, the semiconductor layer, and the second electrode layer.

10. The method of claim 7, wherein the first electrode is transparent.

11. The method of claim 9, wherein the planarization layer is configured to be electrically insulated.

12. The method of claim 9, wherein the planarization layer is configured to be transparent.

13. The method of claim 7, the method further comprising:

patterning the second electrode layer and the semiconductor layer such that an opening is formed to the first electrode layer,

depositing a electrically insulated planarization layer over the first electrode layer, the second electrode layer and the semiconductor layer, and

patterning the planarization layer such that an opening is formed to the first electrode layer through the planarization layer.

14. The method of claim 9, the method further comprising:

patterning the planarization layer such that an opening is formed to the second electrode layer.