Peripheral interface alert message for downstream device

• US 7,970,958 B2
• Filed: 06/20/2005
• Issued: 06/28/2011
• Est. Priority Date: 06/20/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Puffer, David, Singh, Ajai K.
• Primary Examiner(s): Tsai; Henry W
• Assistant Examiner(s): Snyder; Steven G
• Application Number:
  US11/156,838
• Publication Number:
  US 20060288098A1
• Time in Patent Office: 2,199 Days
• Field of Search: 710/5, 710/15, 710/19, 710/8
• US Class Current: 710/19
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/085 using codes with inherent redundancy, e.g. n-out-of-m codes
• CPC Class Codes: H04L 41/06 Management of faults, events, alarms or notifications

Abstract

According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a peripheral interface and may not require a response. It may then be determined that an error is associated with the message, and an alert message may be sent from the upstream device to the downstream device via the peripheral interface.

Claims

1. A method comprising:

receiving at an upstream device a message generated by a downstream device, wherein the message is received via a peripheral interface and does not require a response;

determining that the message is corrupted by an error;

upon determining that the received message is corrupted, sending an alert message from the upstream device to the downstream device via the peripheral interface, wherein the peripheral interface is associated with a Peripheral Component Interconnect (PCI) Express bus, and wherein the alert message includes;

a sequence number of the last packet to have been successfully processed by the upstream device prior to the error,

information associated with an uncorrectable error status register, and

a PCI Express vendor-defined message type-1 packet;

sending a completion message from the upstream device to the downstream device to indicate that the message was not successful in addition to sending the alert message; and

directly outputting, by the downstream device, debug information associated with the error for debugging the error.

2. The method of claim 1, wherein the upstream device is to communicate with (i) the downstream device via the peripheral interface and (ii) a processor via another interface.

3. The method of claim 1, wherein the upstream device is associated with at least one of:

(i) a root complex, (ii) a memory controller hub, (iii) a graphics memory controller hub, (iv) a chipset, or (v) a switch.

4. The method of claim 1, wherein the received message is associated with a PCI Express posted request.

5. The method of claim 1, wherein the determined error comprises at least one of:

(i) a correctable PCI Express error, (ii) a non-correctible fatal PCI Express error, or (iii) a non-correctable non-fatal PCI Express error.

6. The method of claim 1, further comprising:

receiving the alert message at the downstream device, wherein the downstream device generates the debug information in response to receiving the alert message.

7. The method of claim 6, further comprising:

responding to the alert message at the downstream device, wherein responding further comprises the downstream device re-setting itself.

13. The method of claim 1, wherein the determining further comprises determining the error occurred during transmission of the message from the downstream device.

14. The method of claim 1, wherein the alert message information comprises requester identifier information including at least one of a bus number, a requester device number or a function number indicative of the downstream device associated with the message determined to be corrupted.

15. The method of claim 1, wherein the alert message information comprises an identifier indicating the alert message to be an alert message.

8. An apparatus including:

an input port to receive a request from a downstream peripheral, wherein the request does not require a response, and wherein the apparatus is to be coupled to the downstream peripheral via an interface, wherein the interface is associated with a Peripheral Component Interconnect (PCI) Express bus;

an error detector to detect that the received request is corrupted by an error during transmission of the request from the downstream peripheral; and

an output port to send a completion message in addition to an alert message to the downstream peripheral via the interface, wherein the alert message is sent upon the detecting that the received request is corrupted, wherein the completion message indicates that the request was not successful, wherein the downstream device directly outputs information associated with the error for debugging the error, and wherein the alert message includes;

a sequence number of the last packet to have been successfully processed by the apparatus prior to the error,

data associated with an uncorrectable error status register,

a PCI Express vendor-defined message type-1 packet.

9. The apparatus of claim 8, wherein the request is associated with a Peripheral Component Interconnect (PCI) Express posted transaction.

16. The apparatus of claim 8, wherein the apparatus is to be coupled to a processor via a second interface separate from the interface coupling the apparatus to the downstream peripheral.

17. The apparatus of claim 8, wherein the alert message information comprises requester identifier information including at least one of a bus number, a requester device number or a function number indicative of the downstream device associated with the message determined to be corrupted.

18. The apparatus of claim 8, wherein the alert message information comprises an identifier indicating the alert message to be an alert message.

10. An apparatus comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

detecting, at a root complex, that a message received from an endpoint device is corrupted by an error, wherein the root complex is to;

communicate with the endpoint device via a peripheral interface, wherein the peripheral interface is associated with a Peripheral Component Interconnect (PCI) Express bus, and

communicate with a processor via another interface;

upon detecting that the received message is corrupted, transmitting an alert message to the endpoint device via the peripheral interface, wherein the alert message includes;

a sequence number of the last message to have been successfully processed by the root complex prior to the error,

information associated with an uncorrectable error status register, and

a PCI Express vendor-defined message type-1 packet;

sending a completion message to the endpoint device to indicate that the message was not successful in addition to sending the alert message; and

directly outputting, by the endpoint device, information associated with the error for debugging the error.

11. A system comprising:

an endpoint adapted to transmit a request via a peripheral interface;

an interface device coupled to the peripheral interface to receive the request, to detect that the request is corrupted by an error, and upon detecting the request is corrupted, to transmit an alert message to the endpoint via the peripheral interface, wherein the peripheral interface is associated with a Peripheral Component Interconnect (PCI) Express bus, wherein the interface device sends a completion message to indicate that the request was not successful in addition to sending the alert message, wherein the alert message includes;

a sequence number of the last packet to have been successfully processed by the interface device prior to the error,

information associated with an uncorrectable error status register,

a PCI Express vendor-defined message type-1 packet; and

a battery to provide power to the endpoint and the interface when the system is turned off,

wherein the endpoint device is configured to directly output information associated with the error for debugging the error.

12. The system of claim 11, wherein the system is associated with at least one of:

(i) a personal computer, (ii) a mobile computer, (iii) a server, (iv) a wireless device, (v) a game device, or (vi) a media device.

19. The system of claim 11, wherein the interface device is further coupled to a processor via a second interface separate from the peripheral interface.

20. The system of claim 11, wherein the alert message information comprises requester identifier information including at least one of a bus number, a requester device number or a function number indicative of the downstream device associated with the message determined to be corrupted.