Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures

• US 7,970,980 B2
• Filed: 12/15/2004
• Issued: 06/28/2011
• Est. Priority Date: 12/15/2004
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kuesel, Jamie Randall, Hillier, Philip Rogers III, Kirscht, Joseph Allen
• Primary Examiner(s): Thomas; Shane M
• Assistant Examiner(s): Chrzanowski; Matthew R
• Application Number:
  US11/013,149
• Publication Number:
  US 20060129741A1
• Time in Patent Office: 2,386 Days
• Field of Search: 711/5, 711/154, 711/E12.078, 711/E12.081
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.

Claims

1. A memory controller for a digital device, comprising:

an interface for communicating with a plurality of memory modules embodying an addressable memory;

logic receiving memory addresses for processing by said digital device;

memory access logic which accesses memory locations in said addressable memory responsive to receiving said memory addresses, said memory access logic supporting a plurality of different configurations of said memory modules embodying said addressable memory and, for each said configuration of said memory modules, decoding a memory address to a plurality of physical parameter selections representing physical parameters of said addressable memory according to a respective corresponding decoding map of a plurality of decoding maps, said plurality of physical parameter selections including a row select and a column select representing a row and column respectively of memory cell arrays in said memory modules embodying said addressable memory;

wherein, for a first subset of said plurality of different configurations of said memory modules, said first subset being fewer than all of said plurality of different configurations of said memory modules, said memory access logic produces a decoded selection of a first subset of said plurality of physical parameter selections according to the decoding map corresponding to the configuration, said first subset of physical parameter selections not including said column select, said first subset of physical parameter selections being decoded from at least a portion of said memory address, before said memory access logic produces said column select from at least a portion of said memory address; and

wherein, for a second subset of said plurality of different configurations of said memory modules, said second subset being fewer than all of said plurality of different configurations of said memory modules, said first and second subsets of said plurality of different configurations of said memory modules being disjoint, said memory access logic produces a decoded selection of said first subset of said plurality of physical parameter selections according to the decoding map corresponding to the configuration at substantially the same time that said memory access logic produces said column select from at least a portion of said memory address.

2. The memory controller of claim 1,

wherein said digital device comprises a main memory which is distributed as a plurality of local memories, each local memory being accessed using a separate respective memory controller;

wherein said main memory is addressable using real addresses, each real address specifying a unique data location in said main memory; and

wherein each said memory controller translates real addresses to corresponding local addresses, each local address specifying a unique data location in the respective local memory associated with each memory controller, wherein at least some local addresses are duplicated in different local memories.

3. The memory controller of claim 2,

wherein a first subset of address bits of each said local address is identical to a first subset of address bits of the corresponding real address from which the local address was translated;

wherein a first subset of decode logic decodes each said first subset of address bits of a respective real address to a corresponding said first subset of said plurality of physical parameter selections, each said first subset of address bits of a respective real address being input to said first subset of decode logic before the respective real address is translated to a corresponding local address; and

wherein a second subset of decode logic decodes at least a portion of said corresponding local address to said column select after the respective real address corresponding to said corresponding local address is translated to said corresponding local address.

4. The memory controller of claim 1, wherein said first subset of said plurality of physical parameter selections comprises at least one of the set consisting of:

(a) a memory port select, (b) a memory chip group select; and

(c) an internal memory bank select.

5. A digital data processing system, comprising:

at least one processor;

a plurality of memory modules embodying a main memory;

a communications medium for communicating data between said at least one processor and said main memory; and

memory access control logic controlling access by said at least one processor to said main memory, said memory access control logic supporting a plurality of different configurations of said memory modules embodying said main memory and, for each said configuration of said memory modules, decoding a memory address to a plurality of physical parameter selections representing physical parameters of said main memory according to a respective decoding map of a plurality of decoding maps;

wherein said memory access control logic comprises first decode logic and second decode logic, said first decode logic decoding a first portion of said memory address to a first subset of said plurality of physical parameter selections according to a first subset of said plurality of decoding maps, said first subset of decoding maps being fewer than all of said plurality of decoding maps, said second decode logic decoding said first portion of said memory address to a second subset of said plurality of physical parameter selections according to a second subset of said plurality of decoding maps, said second subset of decoding maps being fewer than all of said plurality of decoding maps, said first and second subsets of said plurality of decoding maps being disjoint;

wherein said first decode logic produces said first subset of said plurality of physical parameter selections from an input memory address with less delay than second decode logic produces said second subset of said plurality of physical parameter selections from an input memory address.

6. The digital data processing system of claim 5,

wherein said first portion of said memory address is less than all of said memory address;

and

wherein said second decode logic further decodes a second portion of said memory address different from said first portion according to said first subset of said plurality of decoding maps and said second subset of said plurality of decoding maps.

7. The digital data processing system of claim 5,

wherein said first subset of physical parameter selections are decoded from consistent bit positions of said memory address for a plurality of different said configurations of said memory modules according to said first subset of decoding maps;

and

wherein said second subset of physical parameter selections are not decoded from consistent bit positions of said memory address for a plurality of different said configurations of said memory modules according to said second subset of decoding maps.

8. The digital data processing system of claim 5,

wherein said system comprises a plurality of processors;

wherein said main memory is distributed as a plurality of local memories, each local memory being associated with one or more respective processors of said plurality of processors; and

wherein said memory access control logic is distributed as a plurality of local memory controllers, each local memory controller being associated with a respective one of said plurality of local memories.

9. The digital data processing system of claim 8,

wherein each said processor generates real addresses of corresponding main memory locations to be accessed, each real address specifying a unique data location in said main memory;

and

wherein each said local memory controller translates real addresses generated by processors to local addresses, each local address specifying a unique data location in the respective local memory associated with each local memory controller, wherein at least some local addresses are duplicated in different local memories.

10. The digital data processing system of claim 5, wherein said first subset of said plurality of physical parameter selections comprises at least one of the set consisting of:

(a) a memory port select, (b) a memory chip group select; and

(c) an internal memory bank select.