Apparatus and methods for stabilization of processors, operating systems and other hardware and/or software configurations

• US 7,971,104 B2
• Filed: 09/24/2007
• Issued: 06/28/2011
• Est. Priority Date: 10/24/2006
• Status: Active Grant

• Current Assignee: Avraham Yinnon Haviv, Shlomi Dolev
• Original Assignee: Avraham Yinnon Haviv, Shlomi Dolev
• Inventors: Haviv, Avraham Yinnon, Dolev, Shlomi
• Primary Examiner(s): Baderman; Scott T
• Assistant Examiner(s): PATEL, KAMINI B
• Application Number:
  US11/902,572
• Publication Number:
  US 20080098205A1
• Time in Patent Office: 1,373 Days
• Field of Search: 714/55
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40

Abstract

Apparatus and methods for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, comprising providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor, in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states. Also described are applications for stabilization of operating systems and other hardware or software configurations, apparatus and methods for ensuring eventual invariance of software executed by a processor, and apparatus and methods for enforcing fixed software configurations.

Claims

1. A method for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, the method comprising:

providing self-stabilizing watchdog hardware that, with given timing, interacts with the processor in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states;

providing a processor utilizing system which utilizes said processor, said processor utilizing system comprising a virtual machine monitor executing a plurality of virtual systems which all share said processor;

providing at least one design software segment operative to perform a check determining whether a current state of said processor utilizing system is consistent; and

ensuring periodic execution of said check by at least one design software segment,

wherein said processor is operative to serve an element of a communication network having a communication protocol and a bandwidth and wherein said plurality of virtual systems executed by said virtual machine monitor comprises

an operating system of said communication network element, and

a communication protocol manager which manages the communication protocol,

thereby generating a plurality of separate and separately stabilizing virtual communication layers each having a communication capacity, and each secured from influence of the others'"'"' activity.

2. The method according to claim 1, further comprising resetting the processor at intervals, using said self-stabilizing watchdog hardware.

3. The method according to claim 2, wherein said resetting occurs responsive to a software request.

4. The method according to claim 3, wherein said resetting is repeated if a predetermined time interval has elapsed without software requests.

5. The method according to claim 1, wherein the interaction sequence comprises provision of notification to the processor that said trigger is about to become operative.

6. The method according to claim 5, further comprising providing a set of at least one software segments operative to store information which is to survive reset for continued use after reset.

7. The method according to claim 1, further comprising providing a set of at least one software segments operative to store information which is to survive reset for continued use after reset.

8. The method according to claim 7, wherein, anytime during execution of an OS/VMM, the following sequence may occur:

execution of save-code, reset of the processor and execution of restore-code.

9. The method according to claim 1, further comprising providing software segments for execution by said processor after said trigger, said software segments being operative to check whether the current state of the system comprising said processor and said memory device is consistent and if not, to convert said current state into a consistent state.

10. The method according to claim 1, wherein said processor utilizing system comprises an operating system.

11. The method according to claim 1, wherein at least one of the virtual systems executed by the virtualization system comprises a monitoring virtual system which monitors the remaining ones of the virtual systems executed by the virtualization system.

12. The method according to claim 11, wherein the monitoring virtual system has access to all variables accessed by the virtualization system.

13. The method according to claim 1, wherein said element of a communication network comprises a router.

14. The method according to claim 1, further comprising configuring said monitoring virtual system to allot at least a constant minimal share of said bandwidth to said communication protocol manager.

15. The method according to claim 1, wherein if a request is made, the self-stabilizing watchdog hardware continues into a state in which a reset of the processor takes place.

16. The method according to claim 1, wherein exactly one of the virtual systems executed by the virtualization system comprises a monitoring virtual system which monitors the remaining ones of the virtual systems executed by the virtualization system.

17. The method according to claim 16, wherein the monitoring virtual system has access to all variables accessed by the virtualization system.

18. A method for enforcing a fixed software configuration notwithstanding occurrence of transient errors, the method comprising:

in the course of generating software which assigns values to a plurality of variables, defining at least one variable as a configurational variable;

hard-wiring the values of said at least one configurational variable; and

redirecting at least one subsequent access attempt of at least one individual configurational variable, to the hard-wired value of said individual configurational variable.

19. The method according to claim 18, wherein said hard-wiring step is performed when the values of all configuration variables defined in said defining step, are final according to a finality determination criterion.

20. The method according to claim 19, wherein said finality determination criterion comprises an input by a human operator.

21. An apparatus for converting a processor, having a plurality of states and being operative to execute software operations stored in a memory device, into a self-stabilizing processor, the apparatus comprising:

self-stabilizing watchdog hardware that, with given timing, interacts with the processor in accordance with an interaction sequence that includes at least one trigger that sets the processor to a known state from among a set of at least one known states;

a processor utilizing system which utilizes said processor, said processor utilizing system comprising a virtual machine monitor executing a plurality of virtual systems which all share said processor;

at least one design software segment operative to perform a check determining whether a current state of said processor utilizing system is consistent; and

apparatus for ensuring periodic execution of said check by at least one design software segment,

wherein said processor is operative to serve an element of a communication network having a communication protocol and a bandwidth and wherein said plurality of virtual systems executed by said virtual machine monitor comprises

an operating system of said communication network element, and

a communication protocol manager which manages the communication protocol,

thereby generating a plurality of separate and separately stabilizing virtual communication layers each having a communication capacity, and each secured from influence of the others'"'"' activity.