Memory diagnosis method

• US 7,971,112 B2
• Filed: 01/23/2009
• Issued: 06/28/2011
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Murata, Takehiko
• Primary Examiner(s): KERVEROS, DEMETRIOS C
• Application Number:
  US12/358,366
• Publication Number:
  US 20090199056A1
• Time in Patent Office: 886 Days
• Field of Search: 714/710, 714/718, 714/719
• US Class Current: 714/719
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/1208 Error catch memory
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A method of an apparatus for diagnosing a memory including a storing module for storing diagnosis information relating to memory errors in a memory to be diagnosed, the apparatus capable of detecting memory errors, the method includes: testing the memory and detecting a memory error for each of a plurality of areas of the memory; dividing at least one of the areas into a plurality of sub-areas upon detection of a memory error in the at least one of the areas; testing the sub-areas and detecting a memory error for each of the plurality of the sub-areas; counting the number of sub-areas where a memory error is detected; and storing information of the number of the sub-areas where a memory error is detected together with information of the at least one of the areas containing the sub-areas into the storing module.

Claims

1. A method of controlling an apparatus including a memory having a plurality of memory areas, the method comprising:

reading data stored in a one of the memory areas to be tested;

counting a number of occurrences of memory error detected on the basis of data written into each of the memory areas;

when the number of occurrences of memory error of the read memory area exceeds a first predetermined number of occurrences, disabling the counting of the number of occurrences of memory error of a correctable type;

determining whether the memory error of the read memory area has occurred;

enabling the counting performed by a counter to re-count the number of occurrences of memory error of the read memory area, upon determining that no memory error has occurred, and

determining that the memory is defective when the number of occurrences of memory error is greater than or equal to a second predetermined number.

2. The method according to claim 1, further comprising correcting the memory error of the correctable type by using an error correction mechanism.

3. The method according to claim 1, further comprising detecting an uncorrectable memory error for the read memory area in connection with the disabling.

4. The method according to claim 1, wherein the counting is performed at the initiation of the apparatus.

5. An apparatus comprising:

a memory having a plurality of memory areas;

a counter to count a number of occurrences of memory error detected on the basis of data written into the each of the memory areas; and

a processor executing;

reading data stored in a one of the memory areas to be tested,

when a number of occurrences of memory error of the read memory area exceeds a first predetermined number of occurrences, disabling the counting of the number of occurrences of memory error of a correctable type performed by the counter,

determining whether or not the memory error of the read memory area has occurred,

enabling the counting performed by the counter to re-count the number of occurrences of memory error of the read memory area, upon determining that no memory error has occurred, and

determining that the memory is defective when the number of occurrences of memory error is greater than or equal to a second predetermined number.