Method, system, and program product for automated verification of gating logic using formal verification
First Claim
1. A method performed by a computer of testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process, said method comprising:
- generating testbench design code for a device design from a design source containing hardware design language code;
performing, by said computer, a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches, and/or registers within the device design will be stable or unstable under a gating condition;
then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orthen ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition.
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Accused Products
Abstract
Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
45 Citations
23 Claims
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1. A method performed by a computer of testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process, said method comprising:
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generating testbench design code for a device design from a design source containing hardware design language code; performing, by said computer, a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches, and/or registers within the device design will be stable or unstable under a gating condition; then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orthen ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system for testing a multi-domain microelectronic circuit to verify gating rules for a device design containing microelectronic circuits, latches, and/or registers by employing a formal verification process, said system comprising:
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means for generating testbench design code for a device design from a design source containing hardware design language code; means for performing a formal verification process on the testbench design code to determine whether latches and/or registers within a device design will be stable or unstable under a gating condition; means for indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
ormeans for ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A computer program product comprising a non-transitory computer useable storage medium including a computer readable program, the computer readable program when executed on a computer causes the computer to implement a method of testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process, said method comprising the steps of:
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generating testbench design code for a device design from a design source containing hardware design language code; performing a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches and/or registers within the device design will be stable or unstable under a gating condition; then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orthen ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (18, 19, 20, 21, 22, 23)
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Specification