Method for repeated block timing analysis
First Claim
Patent Images
1. A method for designing an integrated circuit, the method comprising:
- receiving, at one or more computer systems, information specifying an integrated circuit that includes a plurality of instances of a repeated block;
analyzing, with one or more processors associated with the one or more computer systems, the integrated circuit using multimode timing analysis treating each instance of the repeated block as a mode; and
generating, with the one or more processors associated with the one or more computer systems, a design for the integrated circuit based on timing information associated with each instance of the repeated block.
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Abstract
In various embodiments, each possible different instance of a repeated block can be concurrently optimized for timing. Each instance of a repeated block may be treated as a mode, such as a functional mode or testing mode, allowing implementation calculations to be performed simultaneously. Using multimode timing analysis, all instances of a repeated block can be analyzed and optimized simultaneously. Based on the multimode analysis, instances of a repeated block may be implemented identically or substantially similarly, which can reduce costs associated with implementing the same block more than once (e.g., impact to schedule, CPU/memory resources, ECOs).
18 Citations
25 Claims
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1. A method for designing an integrated circuit, the method comprising:
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receiving, at one or more computer systems, information specifying an integrated circuit that includes a plurality of instances of a repeated block; analyzing, with one or more processors associated with the one or more computer systems, the integrated circuit using multimode timing analysis treating each instance of the repeated block as a mode; and generating, with the one or more processors associated with the one or more computer systems, a design for the integrated circuit based on timing information associated with each instance of the repeated block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for repeated blocks timing analysis, the method comprising:
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determining, with one or more processors associated with one or more computer systems, one or more modes of operation; defining, with the one or more processors associated with the one or more computer systems, a set of timing requirements associated with each mode in the one or more modes; setting, with the one or more processors associated with the one or more computer systems, a set of timing constraints associated with each mode in the one or more modes; associating, with the one or more processors associated with the one or more computer systems, at least one mode in the one or more modes with an instance of a repeated block; selecting, with the one or more processors associated with the one or more computer systems, one or more cells, implementing buffering, and performing cloning; analyzing, with the one or more processors associated with the one or more computer systems, timing across each of the one or more modes using multimode timing analysis; and generating, with the one or more processors associated with the one or more computer systems, a logic optimization in standard cells based on the multimode timing analysis. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method for repeated blocks timing analysis, the method comprising:
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receiving, at one or more computer systems, information associated with a chip; performing, with one or more processors associated with the one or more computer systems, a timing optimization on the chip; identifying, with the one or more processors associated with the one or more computer systems, one or more repeated blocks in the chip; and performing, with the one or more processors associated with the one or more computer systems, repeated blocks timing analysis on the chip. - View Dependent Claims (18, 19, 20, 21)
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22. A non-transitory computer readable medium configured to store a set of code modules which when executed by a processor of a computer system become operational with the processor for designing an integrated circuit, the non-transitory computer readable medium comprising:
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code for receiving information specifying an integrated circuit that includes a plurality of instances of a repeated block; code for analyzing the integrated circuit using multimode timing analysis treating each instance of the repeated block as a mode; and code for generating a design for the integrated circuit based on timing information associated with each instance of the repeated block. - View Dependent Claims (23)
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24. A system for designing an integrated circuit, the system comprising:
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a processor; and a memory coupled to the processor, the memory configured to store a plurality of instructions which when executed by the processor become operational with the processor to; receive information specifying an integrated circuit that includes a plurality of instances of a repeated block; analyze the integrated circuit using multimode timing analysis treating each instance of the repeated block as a mode; and generate a design for the integrated circuit based on timing information associated with each instance of the repeated block. - View Dependent Claims (25)
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Specification