IC that efficiently replicates a function to save logic and routing resources

• US 7,971,172 B1
• Filed: 03/17/2008
• Issued: 06/28/2011
• Est. Priority Date: 11/07/2005
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Pugh, Daniel J., Caldwell, Andrew
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/050,143
• Time in Patent Office: 1,198 Days
• Field of Search: 716/16, 716/18, 326/38, 326/41, 326/47, 326/101, 713/1, 713/2, 713/100
• US Class Current: 716/117
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.

Claims

1. A method of configuring an integrated circuit (IC) comprising a plurality of reconfigurable logic circuits and a plurality of configurable interconnect circuits, the method comprising:

configuring a particular set of reconfigurable logic circuits to perform a particular set of operations during a first reconfiguration cycle; and

to reduce use of configurable interconnect circuits, configuring the particular set of reconfigurable logic circuits to perform the particular set of operations during a second reconfiguration cycle.

2. The method of claim 1 further comprising configuring the particular set of reconfigurable logic circuits to perform a different set of operations during a third reconfiguration cycle.

3. The method of claim 1, wherein the particular set of reconfigurable logic circuits performs the particular set of operations during consecutive reconfiguration cycles.

4. The method of claim 1, wherein a particular reconfigurable logic circuit is for configurably performing different logic operations during different reconfiguration cycles, wherein a particular configurable interconnect circuit is a reconfigurable interconnect circuit for configurably performing different routing operations during the different reconfiguration cycles.

5. The method of claim 1, wherein the IC further comprises a plurality of sets of input select interconnect circuits for selecting inputs supplied to at least one configurable logic circuit,

wherein the particular set of operations is performed by a set of input select interconnect circuits at least once.

6. An integrated circuit (IC) comprising:

a plurality of reconfigurable logic circuits; and

a plurality of configurable interconnect circuits,

wherein a particular set of reconfigurable logic circuits is configured for;

performing a particular set of operations during one reconfiguration cycle; and

in order to reduce use of configurable interconnect circuits, performing the particular set of operations again during another reconfiguration cycle.

7. The IC of claim 6, wherein the IC implements a design using a primary clock cycle, wherein a reconfiguration cycle is a sub-cycle of the primary clock cycle.

8. The IC of claim 7, wherein the primary clock cycle comprises a plurality of reconfiguration cycles.

9. The IC of claim 6, wherein the particular set of reconfigurable logic circuits receives two identical sets of configuration data that cause the particular set of reconfigurable logic circuits to perform the particular set of operations twice.

10. The IC of claim 6, wherein the IC further comprises a plurality of sets of input select interconnect circuits for selecting inputs supplied to at least one reconfigurable logic circuit,

wherein the particular set of operations is performed by the input select interconnect circuits at least twice.

11. The IC of claim 6 further comprising a plurality of sets of input select interconnect circuits for selecting inputs supplied to at least one reconfigurable logic circuit,

wherein the particular set of operations is performed (i) at least once by a set of reconfigurable logic circuits and (ii) at least once by a set of input select interconnect circuits.

12. An integrated circuit (IC) comprising:

a plurality of configurable interconnect circuits; and

a plurality of configurable logic circuits configured for;

performing a particular set of operations on a particular set of input values during a first operational period of the IC; and

performing the particular set of operations on the particular set of input values during a second operational period of the IC in order to reduce use of the configurable interconnect circuits.

13. The IC of claim 12, wherein the performing of the particular set of operations during the second operational period does not increase an overall execution of operations by the IC.

14. The IC of claim 12, wherein the plurality of configurable logic circuits are configured to perform a second set of operations during a third operational period of the IC, wherein the second set of operations is based on a different set of input values than the particular set of input values.

15. The IC of claim 12, wherein the particular set of operations comprises a mathematical operation.

16. The IC of claim 12, wherein the particular set of operations comprises a logic operation.

17. The IC of claim 12, wherein a particular set of configurable logic circuits performs (i) a mathematical operation during at least one operational period and (ii) a logic operation during at least another operational period.

18. The IC of claim 17, wherein the particular set of configurable logic circuits receives, (i) during said at least one operational period, a first configuration data set that causes the particular set of configurable logic circuits to perform the mathematical operation, and, (ii) during said at least another operational period, a second configuration data set that causes the particular set of configurable logic circuits to perform the logic operation.

19. A method for configuring an integrated circuit (IC) comprising a plurality of configurable interconnect circuits and a plurality of configurable logic circuits, said method comprising:

configuring a particular set of configurable interconnect circuits to supply a set of input values to a particular set of configurable logic circuits; and

configuring the particular set of configurable logic circuits to perform (i) a particular set of operations on the set of input values during a first operational period of the IC, and (ii) the particular set of operations on the set of input values during a second operational period of the IC in order to reduce use of the configurable interconnect circuits.

20. The method of claim 19, wherein the particular set of configurable logic circuits does not receive any input values from any configurable interconnect circuit during the second operational period of the IC.