Congestion aware pin optimizer

• US 7,971,174 B1
• Filed: 09/18/2008
• Issued: 06/28/2011
• Est. Priority Date: 09/18/2008
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fangaria, Pawan, Khalsa, Mahendra Singh, Gupta, Vandana, Ghosh, Sanjib, Marwah, Hitesh
• Primary Examiner(s): Levin; Naum
• Application Number:
  US12/233,414
• Time in Patent Office: 1,013 Days
• Field of Search: 716/118, 716/129, 716/130
• US Class Current: 716/129
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.

Claims

1. In a circuit design process, a method of reducing routing congestion, comprising:

performing a block placement operation;

performing an initial pin optimization for the block placement;

performing global routing based upon the initial pin optimization;

generating congestion data from the global routing; and

in an automatic process, re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization.

2. The method of claim 1, further comprising:

determining, based upon the congestion data, whether a level of congestion is acceptable, wherein the re-optimizing the pins is performed in response to determining that the level, of congestion is not acceptable.

3. The method of claim 1, further comprising:

updating the congestion data for the re-optimized pins using the global routing; and

determining, based upon the updated congestion data, whether a level of congestion is acceptable.

4. The method of claim 3, further comprising:

in response to determining that the level of congestion is not acceptable, running a pin optimization based upon the updated congestion data; and

in response to determining that the level of congestion is acceptable, continuing with chip finishing.

5. The method of claim 1, wherein the design process is for a custom layout design process.

6. The method of claim 1, wherein said re-optimizing the pins includes:

identifying cells in the design having a congestion value exceeding a user provided target value; and

re-spacing pins for cells exceeding the target value.

7. A computer program product to reduce routing congestion in a circuit design process, including a storage device comprising executable instructions, the computer program product comprising instructions for performing a method including:

performing a block placement operation;

performing an initial pin optimization for the block placement;

performing global routing based upon the initial pin optimization;

generating congestion data from the global routing; and

in an automatic process, re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization.

8. The computer program product claim 7, wherein the method further includes:

determining, based upon the congestion data, whether a level of congestion is acceptable, wherein the re-optimizing the pins is performed in response to determining that the level of congestion is not acceptable.

9. The computer program product claim 7, wherein the method further includes:

updating the congestion data for the re-optimized pins using the global routing; and

determining, based upon the updated congestion data, whether a level of congestion is acceptable.

10. The computer program product claim 9, wherein the method further includes:

in response to determining that the level of congestion is not acceptable, running a pin optimization based upon the updated congestion data; and

in response to determining that the level of congestion is acceptable, continuing with chip finishing.

11. The computer program product claim 7, wherein the design process is for a custom layout design process.

12. The computer program product claim 7, wherein said re-optimizing the pins includes:

identifying cells in the design having a congestion value exceeding a user provided target value; and

re-spacing pins for cells exceeding the target value.

13. A system for a design process of an integrated circuit containing multiple devices, comprising:

a user interface for viewing representations of the integrated circuit on a display; and

at least one processing unit including circuitry to a perform a process to reduce routing congestion in a circuit design process, the process including;

performing a block placement operation;

performing an initial pin optimization for the block placement;

performing global routing based upon the initial pin optimization;

generating congestion data from the global routing; and

re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization.

14. The system of claim 13, wherein the process further includes:

determining, based upon the congestion data, whether a level of congestion is acceptable, wherein the re-optimizing the pins is performed in response to determining that the level of congestion is not acceptable.

15. The system of claim 13, wherein the process further includes:

updating the congestion data for the re-optimized pins using the global routing; and

determining, based upon the updated congestion data, whether a level of congestion is acceptable.

16. The system of claim 15, wherein the process further includes:

in response to determining that the level of congestion is not acceptable, running a pin optimization based upon the updated congestion data; and

in response to determining that the level of congestion is acceptable, continuing with chip finishing.

17. The system of claim 13, wherein the design process is for a custom layout design process.

18. The system of claim 13, wherein said re-optimizing the pins includes:

identifying cells in the design having a congestion value exceeding a user provided target value; and

re-spacing pins for cells exceeding the target value.