Congestion aware pin optimizer
First Claim
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1. In a circuit design process, a method of reducing routing congestion, comprising:
- performing a block placement operation;
performing an initial pin optimization for the block placement;
performing global routing based upon the initial pin optimization;
generating congestion data from the global routing; and
in an automatic process, re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization.
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Abstract
A circuit design process for the reduction of routing congestion is described. This process includes a block placement operation, an initial pin optimization for the block placement, and global routing based upon the initial pin optimization. Congestion data is generated from the global routing and, in an automated process, the pins are re-optimized, based upon the congestion data. This process can be used as part of a custom layout design process, for example.
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Citations
18 Claims
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1. In a circuit design process, a method of reducing routing congestion, comprising:
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performing a block placement operation; performing an initial pin optimization for the block placement; performing global routing based upon the initial pin optimization; generating congestion data from the global routing; and in an automatic process, re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computer program product to reduce routing congestion in a circuit design process, including a storage device comprising executable instructions, the computer program product comprising instructions for performing a method including:
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performing a block placement operation; performing an initial pin optimization for the block placement; performing global routing based upon the initial pin optimization; generating congestion data from the global routing; and in an automatic process, re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A system for a design process of an integrated circuit containing multiple devices, comprising:
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a user interface for viewing representations of the integrated circuit on a display; and at least one processing unit including circuitry to a perform a process to reduce routing congestion in a circuit design process, the process including;
performing a block placement operation;
performing an initial pin optimization for the block placement;
performing global routing based upon the initial pin optimization;
generating congestion data from the global routing; and
re-optimizing pins based upon the congestion data, wherein one or more pin locations are moved with respect to their block locations from the initial pin optimization. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification