Top-gate thin-film transistors using nanoparticles and method of manufacturing the same

• US 7,972,931 B2
• Filed: 01/17/2007
• Issued: 07/05/2011
• Est. Priority Date: 03/30/2006
• Status: Active Grant

• Current Assignee: Korea University Industrial & Academic Collaboration Foundation
• Original Assignee: Korea University Industrial & Academic Collaboration Foundation
• Inventors: Jang, Jae-Won, Kim, Dong-won, CHO, Kyoung-Ah, Kim, Sangsig
• Primary Examiner(s): Phung, Anh
• Assistant Examiner(s): LULIS, MICHAEL P
• Application Number:
  US11/623,775
• Publication Number:
  US 20070228376A1
• Time in Patent Office: 1,630 Days
• Field of Search: 257/78, 257/288, 257/410, 257/E29.296, 257/E21.535, 438/151, 438/285, 438/287, 438/293, 977/773, 977/824, 977/892, 977/936
• US Class Current: 438/293
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10S 977/773 Nanoparticle, i.e. structure having three dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/824 Group II-VI nonoxide compounds, e.g. CdxMnyTe
• CPC Class Codes: Y10S 977/892 Liquid phase deposition
• CPC Class Codes: Y10S 977/936 in a transistor or 3-terminal device

Abstract

The present invention relates to a method of manufacturing thin-film transistors using nanoparticles and thin film transistors manufactured by the method. A hydrophilic buffer layers are deposited on the substrates to facilitate formation of nanoparticle films. Sintered nanoparticles are used as an active layer and dielectric materials of high dielectric coefficient are also used as a gate dielectric layer to form a top gate electrode on the gate dielectric layer, thereby enabling low-voltage operation and low-temperature fabrication.

Claims

1. A method of manufacturing thin-film transistors using nanoparticles, comprising the steps of:

depositing a buffer layer on a substrate using a hydrophilic material;

forming a nanoparticle film on the buffer layer ;

sintering nanoparticle films on the buffer layer;

forming a source and drain electrodes on the nanoparticle film;

forming a gate dielectric film by depositing a dielectric material on the nanoparticle film with the source and drain electrodes formed thereon; and

forming a top-gate electrode on the gate dielectric film,

wherein the step of forming a nanoparticle film comprises the steps of;

preparing a nanoparticle solution by dispersing nanoparticles into a solvent;

mixing a precipitating agent with the nanoparticle solution; and

depositing the nanoparticle solution containing the precipitating agent on the substrate.

2. The method as claimed in claim 1, wherein the substrate is selected from the group consisting of silicon substrates, glass substrates and flexible substrates.

3. The method as claimed in claim 2, wherein the flexible substrate includes a plastic substrate.

4. The method as claimed in claim 3, wherein the plastic substrate is one of PET (Polyethylene Terephthalate), PEN (Polyethyle Napthalate), PC (Polycarbonate) and PES (Polyether Sulfone).

5. The method as claimed in claim 1, wherein the buffer layer is formed of a hydrophilic inorganic material or a hydrophilic organic material.

6. The method as claimed in claim 5, wherein the hydrophilic inorganic material is selected from the group consisting of Al₂O₃, HfO₂, Ta₂O₅, La₂O₃ and SiO₂.

7. The method as claimed in claim 6, wherein the hydrophilic inorganic material is formed using an atomic layer deposition (ALD) method or a sputtering method.

8. The method as claimed in claim 5, wherein the organic material is selected from the group consisting of AIDCN, polyaniline, Cd-AA(Arachidate), PVP, PVA and PEDOT.

9. The method as claimed in claim 8, wherein a surface of the organic material is made hydrophilic through an ultraviolet process using O₃ as a reaction gas or a plasma process using O₂ as a reaction gas.

10. The method as claimed in claim 9, wherein the organic material is deposited through any one of a spin coating method, a spraying method and a printing method.

11. The method as claimed in claim 1, wherein the buffer layer has a thickness of 2 to 20 nm.

12. The method as claimed in claim 1, wherein the buffer layer is deposited on the substrate at a temperature of 100 to 150°

C.

13. The method as claimed in claim 1, wherein the nanoparticles are selected from the group consisting of HgTe, HgSe, HgS, CdTe, CdSe, CdS, ZnTe, ZnSe, ZnS, PbTe, PbSe, PbS and ZnO.

14. The method as claimed in claim 1, wherein the nanoparticle solution containing the precipitating agent is deposited on the substrate through any one of a spin coating method, a deep coating method, a stamping method, a spraying method and a printing method.

15. The method as claimed in claim 1, wherein the sintering step is carried out for 10 to 200 minutes at a temperature of 100 to 185°

C.

16. The method as claimed in claim 1, wherein the gate insulation film is formed by depositing a dielectric material of high dielectric constant on the nanoparticle film, and the dielectric material is an inorganic material selected from the group consisting one of Al₂O₃, HfO₂, Ta₂O₅, La₂O₃, and SiO₂, or an organic material selected from the group consisting of AIDCN, polyaniline, Cd-AA(Arachidate), PVP, PVA, and PEDOT.

17. The method as claimed in claim 16, wherein when the dielectric material of high dielectric constant is deposited on the nanoparticle film, the substrate has a temperature of 100 to 185°

C. and the gate dielectric film has a thickness of 10 to 500 nm.