Semiconductor package structure and method for manufacturing the same
First Claim
1. A semiconductor package structure, comprising:
- a substrate unit comprising a circuit structure formed thereon and a chip mounting area defined thereupon, the circuit structure having a plurality of bonding pads and a plurality of test pads, each of the bonding pads being arranged within the chip mounting area and connected to each of the test pads; and
a first chip stack structure, comprising a plurality of chips, each of the chips having an upper surface, a bottom surface opposite to the upper surface, and a plurality of through silicon plugs disposed therein to form electrical interconnections between the upper surface and the bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the upper surface or the bottom surface, and the plurality of through silicon plugs of two adjacent chips being electrically connected through the first electrodes respectively;
wherein the first chip stack structure is mounted on the chip mounting area of the substrate unit and at least a portion of the through silicon plugs are electrically connected to the bonding pads, and the plurality of test pads are arranged outside of the chip mounting area.
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Accused Products
Abstract
Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
33 Citations
44 Claims
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1. A semiconductor package structure, comprising:
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a substrate unit comprising a circuit structure formed thereon and a chip mounting area defined thereupon, the circuit structure having a plurality of bonding pads and a plurality of test pads, each of the bonding pads being arranged within the chip mounting area and connected to each of the test pads; and a first chip stack structure, comprising a plurality of chips, each of the chips having an upper surface, a bottom surface opposite to the upper surface, and a plurality of through silicon plugs disposed therein to form electrical interconnections between the upper surface and the bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the upper surface or the bottom surface, and the plurality of through silicon plugs of two adjacent chips being electrically connected through the first electrodes respectively; wherein the first chip stack structure is mounted on the chip mounting area of the substrate unit and at least a portion of the through silicon plugs are electrically connected to the bonding pads, and the plurality of test pads are arranged outside of the chip mounting area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for manufacturing a semiconductor package structure, comprising the following steps of:
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providing a substrate, the substrate comprising a plurality of substrate units, each of the substrate units comprising a circuit structure formed thereon and a chip mounting area defined thereupon, the circuit structure having a plurality of bonding pads and a plurality of test pads, each of the bonding pads being arranged within the chip mounting area and connected to each of the test pads, and the test pads being arranged outside of the chip mounting area; forming a first sealing layer on the chip mounting area; attaching a first chip on the chip mounting area by the first sealing layer, the first chip having a first upper surface, a first bottom surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the first upper surface and the first bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the first upper surface or the first bottom surface; electrically connecting at least a portion of the plurality of through silicon plugs of the first chip to the bonding pads, wherein a space between the first chip and the substrate unit is filled by the first sealing layer; forming a second sealing layer on the first upper surface; attaching a second chip on the first upper surface by the second sealing layer, the second chip having a second upper surface, a second bottom surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the second upper surface and the second bottom surface, each of the through silicon plugs comprising a second electrode jutting out from one of the second upper surface or the second bottom surface; and electrically connecting at least a portion of the plurality of through silicon plugs of the second chip to the corresponding through silicon plugs of the first chip, wherein a space between the first chip and the second chip is filled by the second sealing layer. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
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28. A semiconductor package structure, comprising:
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a first semiconductor chip having a first upper surface, a first bottom surface, a plurality of test pads, a first chip mounting area defined on the first upper surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the first upper surface and the first bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the first upper surface or the first bottom surface, each of the test pads being arranged outside of the first chip mounting area and connected to each of the through silicon plugs; a second semiconductor chip having a second upper surface, a second bottom surface, a plurality of test pads, a second chip mounting area defined on the second upper surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the second upper surface and the second bottom surface, each of the through silicon plugs comprising a second electrode jutting out from one of the second upper surface or the second bottom surface, each of the test pads being arranged outside of the second chip mounting area and connected to each of the through silicon plugs; and wherein the second semiconductor chip is mounted on the first chip mounting area and at least a portion of the plurality of through silicon plugs of the second semiconductor chip are electrically connected to the corresponding through silicon plugs of the first semiconductor chip. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35)
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36. A method for manufacturing a semiconductor package structure, comprising the following steps of:
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providing a first semiconductor element comprising at least one chip, the at least one chip having a first upper surface, a first bottom surface, a plurality of test pads, a first chip mounting area defined on the first upper surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the first upper surface and the first bottom surface, each of the through silicon plugs comprising a first electrode jutting out from one of the first upper surface or the first bottom surface, each of the test pads being arranged outside of the first chip mounting area and connected to each of the through silicon plugs; forming a first sealing layer on the first chip mounting area; attaching a second semiconductor element on the first chip mounting area by the first sealing layer, the second semiconductor element having a second upper surface, a second bottom surface, a plurality of test pads, a second chip mounting area defined on the second upper surface and a plurality of through silicon plugs disposed therein to form electrical interconnections between the second upper surface and the second bottom surface, each of the through silicon plugs comprising a second electrode jutting out from one of the second upper surface or the second bottom surface, each of the test pads being arranged outside of the second chip mounting area and connected to each of the through silicon plugs; and electrically connecting at least a portion of the plurality of through silicon plugs of the second semiconductor element to the corresponding through silicon plugs of the first semiconductor element, wherein a space between the first semiconductor element and the second semiconductor element is filled by the first sealing layer. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44)
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Specification