Nonvolatile semiconductor memory and method of manufacturing the same

• US 7,973,356 B2
• Filed: 09/30/2008
• Issued: 07/05/2011
• Est. Priority Date: 10/04/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Kikuchi, Takeshi
• Primary Examiner(s): Wilczewski; Mary
• Application Number:
  US12/285,167
• Publication Number:
  US 20090090962A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/E29.3, 257/E29.302, 257/E29.304, 257/E27.103, 257/320, 257/321, 257/319, 257/316, 257/E29.309, 257/324, 257/326, 438/261, 438/267
• US Class Current: 257/324
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first gate electrode formed on the semiconductor substrate through a gate insulating film; a second gate electrode formed in a side direction of the first gate electrode and electrically insulated from the first gate electrode; and an insulating film formed at least between the semiconductor substrate and the second gate electrode to trap electric charge, as an electric charge trapping film. The first gate electrode comprises a lower portion contacting the gate insulating film and an upper portion above the lower portion of the first gate electrode, and a distance between the upper portion of the first gate electrode and the second gate electrode is longer than a distance between the lower portion of the first gate electrode and the second gate electrode.

Claims

1. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a first gate electrode formed on said semiconductor substrate through a gate insulating film;

a second gate electrode, comprising a side portion, formed in a side direction of said first gate electrode and electrically insulated from said first gate electrode; and

an electric charge trapping film formed at least between said semiconductor substrate and said second gate electrode to trap electric charge,

wherein said first gate electrode comprises a lower portion contacting said gate insulating film and an upper portion above said lower portion of said first gate electrode,

wherein a distance between said upper portion of said first gate electrode and said second gate electrode is greater than a distance between said lower portion of said first gate electrode and said second gate electrode, and

wherein said electric charge trapping film and a spacer insulating film are sandwiched between said upper portion of said first gate electrode and said side portion of said second gate electrode.

2. The nonvolatile semiconductor memory device according to claim 1, wherein said electric charge trapping film exists between said first gate electrode and said second gate electrode, as well as between said semiconductor substrate and said second gate electrode.

3. The nonvolatile semiconductor memory device according to claim 2, wherein said electric charge trapping film is provided between said lower portion of said first gate electrode and said second gate electrode.

4. The nonvolatile semiconductor memory device according to claim 1, further comprising:

a silicide layer formed on said first gate electrode.

5. The nonvolatile semiconductor memory device according to claim 4, wherein said silicide layer covers a surface of said upper portion of said first gate electrode.

6. The nonvolatile semiconductor memory device according to claim 4, wherein said silicide layer is provided on a surface of said first gate electrode.

7. The nonvolatile semiconductor memory device according to claim 1, wherein said second gate electrode is provided on each side of said first gate electrode.

8. The nonvolatile semiconductor memory device according to claim 1, wherein a section shape of said first gate electrode in a plane that is perpendicular to said semiconductor substrate and perpendicular to a direction in which said first gate electrode extends on a surface of said semiconductor substrate includes a convex shape.

9. The nonvolatile semiconductor memory device according to claim 1, wherein said distance between said lower portion of said first gate electrode and said second gate electrode is equal to a distance between said second gate electrode and said spacer insulating film.

10. The nonvolatile semiconductor memory device according to claim 1, wherein a distance between said semiconductor substrate and at least one surface of said upper portion of said first gate electrode is greater than a distance between said semiconductor substrate and all surfaces of said second gate electrode.

11. The nonvolatile semiconductor memory device according to claim 1, wherein a distance between said semiconductor substrate and all surfaces of said upper portion of said first gate electrode is less than a distance between said semiconductor substrate and at least one surface of said second gate electrode.

12. A nonvolatile semiconductor memory device, comprising:

a semiconductor substrate;

a first gate electrode formed on said semiconductor substrate through a gate insulating film;

a second gate electrode formed in a side direction of said first gate electrode and electrically insulated from said first gate electrode; and

an insulating film formed at least between said semiconductor substrate and said second gate electrode to trap electric charge, as an electric charge trapping film,

wherein said first gate electrode comprises a lower portion contacting said gate insulating film and an upper portion above said lower portion of said first gate electrode,

wherein a distance between said upper portion of said first gate electrode and said second gate electrode is longer than a distance between said lower portion of said first gate electrode and said second gate electrode, and

wherein said electric charge trapping film comprises an ONO (Oxide Nitride Oxide) film.