Semiconductor device

• US 7,973,410 B2
• Filed: 09/27/2006
• Issued: 07/05/2011
• Est. Priority Date: 10/12/2005
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Green; Telly D
• Application Number:
  US11/527,405
• Publication Number:
  US 20070080374A1
• Time in Patent Office: 1,742 Days
• Field of Search: 340/10.51, 340 21- 28, 340 101- 106, 340/10.5, 3405721-5729, 235/435, 235375-385, 235/492, 365/192
• US Class Current: 257/758
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0676 comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/0811 MIS diodes
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Since a power source voltage is generated from a communication signal in a wireless chip, there is a risk that a large amount of voltage be generated in the wireless chip to electrically destroy a circuit in the case of supplying a strong communication signal. Therefore, the present invention is made with an aim to provide a wireless chip having resistance to a strong communication signal. A wireless chip of the present invention has an element in which a power source wire and a grounding wire are electrically short-circuited if a power source voltage exceeds a voltage at which an electric circuit is destroyed, i.e., exceeds the specified voltage range. Accordingly, a wireless chip of the present invention has resistance to a strong communication signal.

Claims

1. A semiconductor device comprising:

a wireless chip comprising;

a power source circuit for generating a power source voltage by a radio signal,

the power source circuit comprising;

a diode; and

a leak element provided in the power source circuit,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to retain the power source voltage within a specified voltage range by making a first electric resistance of the leak element lower than a second electric resistance of the leak element, and

wherein the first electric resistance is a resistance of the leak element at the time when a voltage which exceeds the specified voltage range generates in the power source circuit,

wherein the second electric resistance is a resistance of the leak element at the time when a voltage which is within the specified voltage range generates in the power source circuit, and

wherein the leak element is electrically connected to the diode.

2. The semiconductor device according to claim 1,

wherein the power source circuit is formed by a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

3. The semiconductor device according to claim 2,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

4. The semiconductor device according to claim 1,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

5. The semiconductor device according to claim 1,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

6. The semiconductor device according to claim 1,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

7. The semiconductor device according to claim 1,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

8. The semiconductor device according to claim 6,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

9. The semiconductor device according to claim 1,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

10. The semiconductor device according to claim 1,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.

11. A semiconductor device comprising:

a wireless chip comprising;

a power source circuit for generating a power source voltage by a radio signal;

the power source circuit comprising;

a diode;

a storage capacitor provided in the power source circuit; and

a leak element provided in the power source circuit,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to retain the power source voltage within a specified voltage range by flowing electric charges accumulated in the storage capacitor to the leak element as current by making a first electric resistance of the leak element lower than a second electric resistance of the leak element, and

wherein the first electric resistance is a resistance of the leak element at the time when a voltage which exceeds the specified voltage range generates in the power source circuit,

wherein the second electric resistance is a resistance of the leak element at the time when a voltage which is within the specified voltage range generates in the power source circuit, and

wherein the leak element is electrically connected to the diode.

12. The semiconductor device according to claim 11,

wherein the power source circuit is formed by a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

13. The semiconductor device according to claim 12,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

14. The semiconductor device according to claim 11,

wherein the power source voltage is a potential difference between a first output terminal and a second output terminal of the storage capacitor.

15. The semiconductor device according to claim 11,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

16. The semiconductor device according to claim 11,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

17. The semiconductor device according to claim 11,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

18. The semiconductor device according to claim 11,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

19. The semiconductor device according to claim 17,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

20. The semiconductor device according to claim 11,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

21. The semiconductor device according to claim 11,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.

22. A semiconductor device comprising:

a wireless chip comprising;

a power source circuit for generating a power source voltage by a radio signal, comprising;

an antenna portion including an antenna and a resonance capacitor;

a rectifying portion including a diode; and

a storage capacitor portion including a storage capacitor and a leak element,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to retain the power source voltage within a specified voltage range by flowing electric charges accumulated in the storage capacitor to the leak element as current by making a first electric resistance of the leak element lower than a second electric resistance of the leak element, and

wherein the first electric resistance is a resistance of the leak element at the time when a voltage which exceeds the specified voltage range generates in the power source circuit,

wherein the second electric resistance is a resistance of the leak element at the time when a voltage which is within the specified voltage range generates in the power source circuit, and

wherein the leak element is electrically connected to the antenna through the diode.

23. The semiconductor device according to claim 22,

wherein the power source circuit is formed by a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

24. The semiconductor device according to claim 23,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

25. The semiconductor device according to claim 22,

wherein the power source voltage is a potential difference between a first output terminal and a second output terminal of the storage capacitor portion.

26. The semiconductor device according to claim 22,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

27. The semiconductor device according to claim 22,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

28. The semiconductor device according to claim 22,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

29. The semiconductor device according to claim 22,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

30. The semiconductor device according to claim 28,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

31. The semiconductor device according to claim 22,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

32. The semiconductor device according to claim 22,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.

33. The semiconductor device according to claim 22,

wherein the rectifying portion has a plurality of the diodes.

34. A semiconductor device comprising:

a wireless chip comprising;

an antenna;

a diode electrically connected to the antenna;

a storage capacitor electrically connected to the diode; and

a leak element electrically connected to the storage capacitor,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to have a first electric resistance at the time when a voltage which exceeds a specified voltage range is applied thereto and a second electric resistance at the time when a voltage which is within the specified voltage range is applied thereto,

wherein the first electric resistance is lower than the second electric resistance, and

wherein the leak element is electrically connected to the antenna through the diode.

35. The semiconductor device according to claim 34,

wherein the leak element is formed by a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

36. The semiconductor device according to claim 35,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

37. The semiconductor device according to claim 34,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

38. The semiconductor device according to claim 34,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

39. The semiconductor device according to claim 34,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

40. The semiconductor device according to claim 34,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

41. The semiconductor device according to claim 39,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

42. The semiconductor device according to claim 34,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

43. The semiconductor device according to claim 34,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.

44. A semiconductor device comprising:

a wireless chip comprising;

a circuit for supplying a power source voltage for the wireless chip, comprising;

an antenna;

a storage capacitor electrically connected to the antenna;

a diode; and

a leak element electrically connected to the storage capacitor,

a clock generating circuit;

a demodulating circuit; and

a modulating circuit,

wherein the circuit for supplying power source voltage supplies a voltage to each circuit,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to have a first electric resistance at the time when a voltage which exceeds a specified voltage range generates in the wireless chip and a second electric resistance at the time when a voltage which is within the specified voltage range generates in the wireless chip,

wherein the first electric resistance is lower than the second electric resistance, and

wherein the leak element is electrically connected to the antenna through the diode.

45. The semiconductor device according to claim 44,

wherein the wireless chip is formed by a thin film transistor having a semiconductor thin film formed over a substrate having an insulating surface.

46. The semiconductor device according to claim 45,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

47. The semiconductor device according to claim 44,

wherein the power source voltage is a potential difference between a first output terminal and a second output terminal of the storage capacitor.

48. The semiconductor device according to claim 44,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

49. The semiconductor device according to claim 44,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

50. The semiconductor device according to claim 44,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

51. The semiconductor device according to claim 44,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

52. The semiconductor device according to claim 50,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

53. The semiconductor device according to claim 44,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

54. The semiconductor device according to claim 44,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.

55. A semiconductor device comprising:

a wireless chip comprising;

a controller;

a CPU;

a ROM;

a RAM;

a circuit for supplying a power source voltage for the wireless chip, comprising;

an antenna;

a storage capacitor electrically connected to the antenna;

a diode; and

a leak element electrically connected to the storage capacitor,

a clock generating circuit;

a demodulating circuit; and

a modulating circuit,

wherein the CPU, the ROM, the RAM, the demodulating circuit, and the modulating circuit are operationally connected to the controller,

wherein the diode is configured to rectify a voltage and output the rectified voltage to the leak element,

wherein the leak element is configured to have a first electric resistance at the time when a voltage which exceeds a specified voltage range generates in the wireless chip and a second electric resistance at the time when a voltage which is within the specified voltage range generates in the wireless chip,

wherein the first electric resistance is lower than the second electric resistance, and

wherein the leak element is electrically connected to the antenna through the diode.

56. The semiconductor device according to claim 55,

wherein the wireless chip is formed by a thin film transistor having semiconductor thin film formed over a substrate having an insulating surface.

57. The semiconductor device according to claim 56,

wherein the substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

58. The semiconductor device according to claim 55,

wherein the power source voltage is a potential difference between a first output terminal and a second output terminal of the storage capacitor.

59. The semiconductor device according to claim 55,

wherein the leak element includes an N-type MOS transistor or a P-type MOS transistor.

60. The semiconductor device according to claim 55,

wherein the leak element includes an N-type memory transistor or a P-type memory transistor.

61. The semiconductor device according to claim 55,

wherein the leak element includes an MIS capacitor comprising a gate insulating film, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

62. The semiconductor device according to claim 55,

wherein the leak element includes an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween, and

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region.

63. The semiconductor device according to claim 61,

wherein film thickness of the gate insulating film in the second region is in the range of 50 to 80% of the film thickness of the gate insulating film in the first region.

64. The semiconductor device according to claim 55,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region, and

wherein the second region overlaps with an end portion of the gate electrode.

65. The semiconductor device according to claim 55,

wherein the leak element has an MIS capacitor comprising a semiconductor thin film, a gate electrode, and a gate insulating film therebetween,

wherein the gate insulating film has at least a first region and a second region having thinner film thickness than the first region,

wherein the first region overlaps with the semiconductor thin film, and

wherein the second region overlaps with an end portion of the semiconductor thin film.