Time resolved radiation assisted device alteration

• US 7,973,545 B2
• Filed: 04/22/2008
• Issued: 07/05/2011
• Est. Priority Date: 04/22/2008
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Asquith, John E., Erington, Kent B.
• Primary Examiner(s): PATEL, PARESH H
• Application Number:
  US12/107,398
• Publication Number:
  US 20090261840A1
• Time in Patent Office: 1,169 Days
• Field of Search: None
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875

Abstract

A method of time resolved radiation assisted device alteration testing of a semiconductor circuit which includes performing spatially resolved radiation assisted circuit testing on the semiconductor circuit while applying a test pattern to determine a pass-fail modulation location, asynchronously scanning the semiconductor circuit with radiation while repeatedly applying the test pattern and providing pass-fail results, combining corresponding pass-fail results provided during the asynchronously scanning to determine a shifted pass-fail modulation indication, determining time shift information between the pass-fail modulation location and the shifted pass-fail modulation indication, and identifying at least one of the test vectors based on the time shift information. The radiation may be a continuous wave laser beam. The time shift information may be determined by scanning an image, incorporating graphics into the image indicating the pass-fail modulation location and the shifted pass-fail modulation indication, and measuring a pixel shift on the scanned image.

Claims

1. A method of time resolved radiation assisted device alteration testing of a semiconductor circuit, comprising:

performing spatially resolved radiation assisted circuit testing on the semiconductor circuit while applying a test pattern comprising a plurality of test vectors to determine a pass-fail modulation location on the semiconductor circuit;

asynchronously scanning the semiconductor circuit with radiation while repeatedly applying the test pattern and providing pass-fail results;

combining corresponding pass-fail results provided during said asynchronously scanning the semiconductor circuit to determine a shifted pass-fail modulation indication;

determining time shift information between the pass-fail modulation location and the shifted pass-fail modulation indication; and

identifying at least one of said plurality of test vectors based on the time shift information.

2. The method of claim 1, wherein said combining corresponding pass-fail information comprises averaging corresponding pass-fail values indicated by a pass-fail signal.

3. The method of claim 1, wherein said asynchronously scanning the semiconductor circuit with radiation comprises scanning the semiconductor circuit with a continuous wave laser.

4. The method of claim 1, wherein said asynchronously scanning the semiconductor circuit with radiation comprises scanning at a selected scan rate which is based on a number of said plurality of test vectors of the test pattern and a test vector rate.

5. The method of claim 1, wherein said determining time shift information comprises:

measuring an offset between the pass-fail modulation location and the shifted pass-fail modulation indication; and

converting the offset to the time shift information based on scanning rate.

6. The method of claim 5, further comprising:

scanning an image of the semiconductor circuit to provide a scanned image;

modifying the scanned image to identify the pass-fail modulation location;

modifying the scanned image to identify the shifted pass-fail modulation indication; and

wherein said measuring an offset comprises measuring a pixel shift on the scanned image.

7. The method of claim 1, wherein said identifying at least one of the plurality of test vectors comprises:

determining a vector shift based on the time shift information and a test vector rate of the test pattern; and

subtracting the vector shift from a total number of test vectors of the test pattern.

8. The method of claim 1, further comprising:

synchronizing an oscilloscope with said asynchronously scanning the semiconductor circuit; and

wherein said combining the pass-fail information comprises averaging pass-fail values to display the time shift information on the oscilloscope.

9. The method of claim 1, wherein said performing spatially resolved radiation assisted circuit testing comprises laser assisted device alteration testing.

10. A method of time resolved laser assisted device alteration testing of a semiconductor circuit, comprising:

performing laser assisted device alteration testing on a selected area of the semiconductor circuit using a test pattern comprising a plurality of test vectors to provide a pass-fail modulation location on the semiconductor circuit;

scanning at least a portion of the selected area of the semiconductor circuit which includes pass-fail modulation location a plurality of times with a laser beam while repeatedly applying the test pattern asynchronous with respect to laser beam scanning and providing a corresponding one of a plurality of pass-fail results for each application of the test pattern;

averaging corresponding ones of said plurality of pass-fail results for providing a shifted pass-fail modulation indication;

determining shift information between the pass-fail modulation location and the shifted pass-fail modulation indication; and

identifying at least one of said plurality of test vectors based on the time shift information.

11. The method of claim 10, further comprising scanning an image of the selected area portion, overlaying a first graphic on the scanned image representing the pass-fail modulation location, overlaying a second graphic on the scanned image representing the shifted pass-fail modulation indication, and displaying the scanned image with the first and second graphics.

12. The method of claim 11, wherein said determining shift information comprises measuring a pixel shift between the first and second graphics on the scanned image.

13. A time resolved radiation assisted device alteration test system for testing circuitry of a semiconductor device, comprising:

a radiation scanning system for scanning the semiconductor device with radiation;

test equipment for applying a test pattern comprising a plurality of test vectors to the semiconductor device and for providing test results according to a time resolved radiation assisted device alteration test procedure;

a control system which controls said radiation scanning system while receiving said test results according to said time resolved radiation assisted device alteration test procedure to enable determination of time shift information between a pass-fail modulation location and a shifted pass-fail modulation indication; and

wherein said time resolved radiation assisted device alteration test procedure causes said radiation scanning system and said test equipment to perform spatially resolved radiation assisted circuit testing of the semiconductor device to identify said pass-fail modulation location, and to perform asynchronous radiation scan testing in which said test equipment repeatedly applies said test pattern to the semiconductor device while providing said test results and while said radiation scanning system asynchronously scans the semiconductor device with radiation to provide said shifted pass-fail modulation indication.

14. The time resolved radiation assisted device alteration test system of claim 13, wherein said radiation scanning system comprises a laser scanning microscope which provides a continuous wave laser beam.

15. The time resolved radiation assisted device alteration test system of claim 13, wherein said test equipment provides a pass-fail signal indicating said test results, wherein said control system causes said radiation scanning system to scan the semiconductor device to provide a scanned image, and wherein said control system is configured to convert said pass-fail signal into test result values incorporated into said scanned image.

16. The time resolved radiation assisted device alteration test system of claim 15, wherein said control system incorporates a first graphic indicating said pass-fail modulation location and a second graphic indicating said shifted pass-fail modulation indication into said scanned image.

17. The time resolved radiation assisted device alteration test system of claim 16, further comprising a display device, wherein said control system displays said scanned image on said display device.

18. The time resolved radiation assisted device alteration test system of claim 13, wherein said control system averages corresponding test results during said asynchronous radiation scan testing into a scan image.

19. The time resolved radiation assisted device alteration test system of claim 13, further comprising an oscilloscope which is synchronized with said radiation scanning system and which receives said test results, wherein said oscilloscope averages corresponding test results of said asynchronous radiation scan testing and displays said time shift information.

20. The time resolved radiation assisted device alteration test system of claim 13, wherein said time resolved laser assisted device alteration test procedure causes said radiation scanning system to scan a reduced-size image incorporating said pass-fail modulation location of the semiconductor device for performing said asynchronous radiation scan testing.