Configuration interface to stacked FPGA

• US 7,973,555 B1
• Filed: 05/28/2008
• Issued: 07/05/2011
• Est. Priority Date: 05/28/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur, Trimberger, Stephen M.
• Primary Examiner(s): Barnie; Rexford N
• Assistant Examiner(s): Hammond; Crystal L
• Application Number:
  US12/128,459
• Time in Patent Office: 1,133 Days
• Field of Search: 326 37- 47, 326/101, 257/777, 257/686, 257/685, 365/51, 365/52, 365/63, 235/462.1
• US Class Current: 326/38
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A semiconductor device includes a field-programmable gate array (“FPGA”) die (202) having a frame address bus (604), a frame data bus (608), and a second integrated circuit (“IC”) die (204) attached to the FPGA die. An inter-chip frame address bus (605) couples at least low order frame address bits of a frame address of a frame between the FPGA die and the second IC die. The inter-chip frame address bus includes a first plurality of contacts (614) formed between the FPGA die and the second IC die. An inter-chip frame data bus couples frame data of the frame between the FPGA die and the second IC die. The inter-chip frame data bus includes a second plurality of contacts (616) formed between the FPGA die and the second IC die.

Claims

1. A semiconductor device comprising:

a first integrated circuit die having, programmable logic, a configuration frame address bus, and a configuration frame data bus;

a second integrated circuit die attached to the first integrated circuit die;

wherein the first integrated circuit die has first and second sides, and the second integrated circuit die has first and second sides;

an inter-chip configuration frame address bus coupling at least low order configuration frame address bits of a configuration frame address of a configuration frame between the first integrated circuit die and the second integrated circuit die, the inter-chip configuration frame address bus including a first plurality of contacts formed between the first integrated circuit die and the second integrated circuit die; and

an inter-chip configuration frame data bus coupling configuration frame data of the configuration frame between the first integrated circuit die and the second integrated circuit die, the inter-chip configuration frame data bus including a second plurality of contacts formed between the first integrated circuit die and the second integrated circuit die;

wherein the second integrated circuit die has programmable logic, and the programmable logic of the first integrated circuit die and the programmable logic of the second integrated circuit die are configurable according to the configuration frame address and the configuration frame data;

wherein the first side of the first integrated circuit die faces the second side of the second integrated circuit die, and the first plurality of contacts and the second plurality of contacts are formed between the first side of the first integrated circuit die and the second side of the second integrated circuit die.

2. The semiconductor device of claim 1 further comprising a decoder in the first integrated circuit die disposed between the configuration frame address bus and a contact between the first integrated circuit die and the second integrated circuit die, the decoder configured to match a bit pattern of high order configuration frame address bits of the configuration frame address and, if the high order configuration frame address bits of the configuration frame address match the bit pattern, to produce a configuration data enable signal coupled to the second integrated circuit die.

3. The semiconductor device of claim 1 wherein the configuration frame data has a configuration frame data bit width and the second plurality of contacts is not less than the configuration frame data bit width.

4. The semiconductor device of claim 1 wherein the configuration frame address has a configuration frame address bit width and the first plurality of contacts is not less than the configuration frame address bit width.

5. The semiconductor device of claim 1 wherein the configuration frame has a configuration frame address with high order configuration frame address bits and low order configuration frame address bits, the high order configuration frame address bits being coupled to a decoder in the first integrated circuit die and the low order configuration frame address bits being coupled to the second integrated circuit die.

6. The semiconductor device of claim 5 wherein the configuration frame address has a configuration frame address bit width and the first plurality of contacts is less than the configuration frame address bit width.

7. The semiconductor device of claim 1 wherein the first integrated circuit die is a first field programmable gate array (FPGA) die and the second integrated circuit die is a second FPGA die.

8. The semiconductor device of claim 1 wherein the first side of the first integrated circuit die is a backside of the first integrated circuit die, and the second side of the second integrated circuit die is a front side of the second integrated circuit die.

9. The semiconductor device of claim 1 wherein the first integrated circuit die includes first logic operating at a first voltage level and the second integrated circuit die includes second logic operating at a second voltage level, the first integrated circuit die further including a level translation circuit between the first logic and the second logic.

10. The semiconductor device of claim 1, wherein the first side of the first integrated circuit die is a front side of the first integrated circuit die, and the second side of the second integrated circuit die is a front side of the second integrated circuit die.

11. The semiconductor device of claim 1, further comprising:

a programmable heterogeneous integration circuit including a programmable logic sub-circuit and an interface sub-circuit, wherein the programmable logic sub-circuit is configurable to implement a logic function, and the interface sub-circuit provides a communication channel between the programmable logic of the first integrated circuit die to the second integrated circuit die; and

selection circuitry coupled to the programmable heterogeneous integration circuit and configured to selectively couple either the programmable logic sub-circuit or the interface sub-circuit to the programmable logic of the first integrated circuit die.