Integrated circuit with delay selecting input selection circuitry

• US 7,973,558 B2
• Filed: 12/14/2009
• Issued: 07/05/2011
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad, Redgrave, Jason
• Primary Examiner(s): Le, Don P
• Application Number:
  US12/637,745
• Publication Number:
  US 20100156456A1
• Time in Patent Office: 568 Days
• Field of Search: 326 37- 41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.

Claims

1. An integrated circuit (IC) comprising:

a) an arrangement of circuits comprising a plurality of configurable circuits for configurably performing a plurality of operations;

b) a debug network with a fixed output capacity for retrieving and outputting data from the arrangement of circuits; and

c) a storage element for storing one of a first bit and a second bit that concurrently arrive at a particular location of the debug network but cannot be outputted concurrently.

2. The IC of claim 1, wherein said second bit is outputted by said debug network after said first bit.

3. The IC of claim 2, wherein said debug network comprises a transport network and wherein said storage element is part of said transport network.

4. The IC of claim 3, wherein the transport network comprises a plurality of multiplexers, wherein the storage element is situated between first and second multiplexers and the storage element is for receiving the second bit from the first multiplexer and holding the second bit for one user cycle to allow the first bit to be outputted by the second multiplexer before the second multiplexer receives the second bit.

5. The IC of claim 3, wherein the transport network comprises multiple layers, each layer comprising a plurality of storage elements for delaying output of bits, wherein one or more layers receive the first bit through the storage element.

6. The IC of claim 1, wherein the first and second bits cannot be outputted concurrently from the debug network because of output congestion at one or more particular locations of the debug network.

7. The IC of claim 6, wherein said output congestion is because at least one of the particular locations is in an output path of at least one of the first bit and the second bit.

8. The IC of claim 6, wherein said output congestion is because at least one of the particular locations is in an output path of bits other than said first bit and said second bit.

9. The IC of claim 1, wherein the storage element delays the arrival of the stored bit at a second particular location of the debug network.

10. An integrated circuit (IC) comprising:

a) a tile array comprising a plurality of configurable circuits for configurably performing a plurality of operations;

b) a debug network comprising a plurality of data lines to route data bits out of the tile array, the debug network having a fixed output capacity; and

c) a plurality of storage elements, positioned along said plurality of data lines, for delaying data bits that concurrently arrive at a particular location of the debug network from the tile array but cannot be outputted concurrently.

11. The IC of claim 10, wherein the storage elements are further for delaying data bits that arrive from the tile array at a congested subcycle until a free subcycle is available.

12. The IC of claim 10, wherein the debug network capacity is divided into discreet slots, wherein each slot is either empty or contains a single data bit.

13. The IC of claim 12, wherein congestion occurs along the debug network when a first data bit is routed through the debug network in a particular slot and a second data bit that is read out at a different subcycle than the first data bit arrives at a circuit of the debug network while the particular slot is using the circuit to transport the first data bit.

14. The IC of claim 10, wherein the debug network further comprises a transport network for transporting data bits out of the IC, said transport network comprising a plurality of storage elements for delaying data bits that are read out during a congested subcycle.

15. The IC of claim 14 further comprising a series of multiplexers for passing data bits along the transport network, each of the multiplexers comprising at least two inputs, wherein a first multiplexer outputs a data bit that had been received at one of the inputs of the first multiplexer to an input of a second multiplexer.

16. The IC of claim 15 further comprising a storage element between an output of the first multiplexer and the input of the second multiplexer, wherein the storage element is for delaying the data bit for at least one subcycle before the data bit is passed to the second multiplexer.

17. The IC of claim 14, wherein the plurality of data lines comprises first and second data lines for carrying data bits in the transport network, wherein the transport network comprises multiple layers, each of the layers for receiving data bits read out of the tile array of the IC, wherein the first data line branches into the second data line for carrying a plurality of data bits from a first layer of the transport network to a second layer of the transport network, said second data line comprising a storage element for delaying each of the data bits by at least one subcycle before carrying the data bits to the second layer of the transport network.

18. The IC of claim 17, wherein the first data line comprises a branch for each layer of the transport network.

19. The IC of claim 17, wherein only one of the layers comprises storage elements for delaying data bits from the tile array.

20. An electronic device comprising:

an integrated circuit (IC) comprising;

a) an arrangement of circuits comprising a plurality of configurable circuits for configurably performing a plurality of operations;

b) a debug network with a fixed output capacity for retrieving and outputting data from the arrangement of circuits; and

c) a storage element for storing one of a first bit and a second bit that concurrently arrive at a particular location of the debug network but cannot be outputted concurrently.

21. The IC of claim 20, wherein the storage element comprises a latch.

22. The IC of claim 20, wherein the storage element comprises a register.

23. The IC of claim 20, wherein the storage element comprises a configurable circuit element.

24. The IC of claim 20, wherein the storage element performs a configurable delay.