Logic based on the evolution of nonlinear dynamical systems

• US 7,973,566 B2
• Filed: 11/23/2010
• Issued: 07/05/2011
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: CDI2, LLC
• Original Assignee: Control Dynamics, Inc., University of Florida Research Foundation, Incorporated (State University System of Florida)
• Inventors: Sinha, Sudeshna, Miliotis, Abraham, Ditto, William L., Murali, Krishnamurthy
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/952,784
• Publication Number:
  US 20110062986A1
• Time in Patent Office: 224 Days
• Field of Search: 326 37- 41, 326/47, 326/104, 708/200, 708/671, 380/263
• US Class Current: 326/104
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence

Abstract

A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Claims

1. A logic gate for implementing a full adder, the logic gate comprising:

a first logic gate input for receiving a first logic gate input signal;

at least a second logic gate input for receiving at least a second logic gate input signal;

a control signal input for receiving at least one control signal;

a first output for producing a first logic gate output signal;

at least a second output for producing a second logic gate output signal;

a first nonlinear updater that operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal, the first nonlinear updater electrically coupled to the logic gate input and comprises a first nonlinear updater output, and configured to apply a first nonlinear function to the input logic gate signal in response to the control signal to produce a first nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the first input logic gate signal;

a first comparator electrically coupled to the first output and the first nonlinear updater output, wherein the first comparator comprising a first comparator input adapted to receive a reference threshold value for producing the first logic gate output signal based on a comparison of the first nonlinear output signal to the reference threshold value;

at least a second nonlinear updater electrically coupled to the first nonlinear output signal, wherein the second nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal, the second nonlinear updater comprising a second nonlinear updater output, and configured to apply a second nonlinear function to the first nonlinear updater output signal in response to the control signal to produce a second nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the second input logic gate signal; and

at least a second comparator electrically coupled to the second out and the second nonlinear updater output, wherein the second comparator comprises a second comparator input adapted to receive a reference threshold value for producing the second logic gate output signal based on a comparison of the second nonlinear output signal to the reference threshold value.

2. The logic gate of claim 1, further comprising:

a third logic gate input for receiving a carry bit signal.

3. The logic gate of claim 1, wherein one of the first logic gate output signal and the second logic gate output signal is a carry bit.

4. The logic gate of claim 1, wherein one of the first logic gate output signal and the second logic gate output signal is a sum bit.