Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers

• US 7,973,596 B2
• Filed: 05/12/2009
• Issued: 07/05/2011
• Est. Priority Date: 05/12/2009
• Status: Active Grant

• Current Assignee: Number 14 B.V.
• Original Assignee: Number 14 B.V.
• Inventors: Eschauzier, Rudy G. H., van Rijn, Nico
• Primary Examiner(s): Pascal; Robert
• Assistant Examiner(s): Nguyen; Khiem D
• Application Number:
  US12/464,572
• Publication Number:
  US 20100289568A1
• Time in Patent Office: 784 Days
• Field of Search: 330/9, 330/124.R, 330/295, 327/124, 327/307
• US Class Current: 330/9
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 2203/45212 the differential amplifier being designed to have a reduced offset
• CPC Class Codes: H03F 3/347 in integrated circuits
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45968 by offset reduction

Abstract

Low-noise, low-power, low drift offset correction in operational and instrumentation amplifiers and amplifiers using the same are disclosed. The amplifiers disclosed use different combinations of chopping and auto-zero techniques. Also disclosed are amplifiers using on-off switches to affect the chopping and auto-zeroing, with unique circuits for driving the switches on the differential input to provide boot-strapped switch controls. Other features are disclosed.

Claims

1. In an amplifier system, a circuit comprising:

a first differential amplifier;

first and second choppers for chopping the input and the output of the first differential amplifier, respectively;

autozero circuitry coupled to the first differential amplifier for autozeroing the first differential amplifier;

the autozero circuitry operating at a first frequency and the choppers operating at a second frequency, the first frequency being twice the second frequency, the second frequency having a 50% duty cycle;

the first frequency having a duty cycle of less than 50%;

each half cycle of the choppers being interrupted while the first differential amplifier is auto-zeroed.

2. The circuit of claim 1 further comprising an amplifier having differential inputs coupled to the first and second differential inputs of the amplifier system and an output coupled to the output amplifier.

3. The circuit of claim 1 wherein the first frequency has a duty cycle of not more than 25%.

4. In an amplifier system, a circuit comprising:

a first differential amplifier;

first and second choppers for chopping the input and the output of the first differential amplifier, respectively;

the first chopper being coupled to the first and second differential inputs of the amplifier system;

a first-switch having a first first-switch state coupling the differential inputs of the first differential amplifier to differential outputs of the first chopper, and a second first-switch state connecting the differential inputs of the first differential amplifier together;

a second differential amplifier, the second differential amplifier having differential inputs, each connected to a circuit ground through a respective capacitance;

differential outputs of the first and second differential amplifiers being coupled in common;

an output amplifier having an input coupled to an output of the second chopper;

a second-switch having a first second-switch state coupling the common outputs of the first and second differential amplifiers to an input of the second chopper, and a second second-switch state coupling the common outputs of the first and second differential amplifiers to the differential inputs of the second differential amplifier;

the first and second switches operating at a first frequency and the choppers operating at a second frequency unequal to the first frequency.

5. The circuit of claim 4 wherein the second frequency is twice the first frequency, and the first and second frequencies each have a 50% duty cycle.

6. The circuit of claim 4 wherein the first frequency is twice the second frequency, the second frequency having 50% duty cycle.

7. The circuit of claim 6 wherein the first frequency has a duty cycle of less than 50%, whereby each half cycle of the choppers is interrupted while the first differential amplifier is auto-zeroed.

8. The circuit of claim 6 wherein the first frequency has a duty cycle of not more than 25%, whereby each half cycle of the choppers is interrupted while the first differential amplifier is auto-zeroed.

9. The circuit of claim 6 further comprising:

third and fourth differential amplifiers, the fourth differential amplifier having differential inputs, each connected to a circuit ground through a respective capacitance, differential outputs of the third and fourth differential amplifiers being coupled in common;

the first-switch when in the first first-switch state also coupling the differential inputs of the third differential amplifier together and coupling the common outputs of the third and fourth differential amplifiers to the differential inputs to the fourth differential amplifier;

the first-switch when in the second first-switch state coupling the differential outputs of the first chopper to the differential inputs of the third differential amplifier and coupling the common differential outputs of the third and fourth differential amplifiers to the differential inputs of the second chopper.

10. The circuit of claim 9 further comprising an amplifier having differential inputs coupled to the first and second differential inputs of the amplifier system and an output coupled to the output amplifier.

11. The circuit of claim 6 wherein:

the first and second switches and the first and second choppers comprise third, fourth and fifth switches, each having an open and a closed state;

the first differential input of the amplifier system being connectable to a first differential input of the first differential amplifier by third and fifth switches, and to a second differential input of the first differential amplifier by the fourth and fifth switches;

the second differential input of the amplifier system being connectable to the first differential input of the first differential amplifier by the fourth switch, and to the second differential input of the first differential amplifier by the third switch;

a first common connection of the outputs of the first and third differential amplifiers being connectable to a first differential input of the differential output amplifier through the third switch and to a second differential input to the differential output amplifier through the fourth switch;

a second common connection of the outputs of the first and second differential amplifiers being connectable to a first input of the differential output amplifier through the fourth switch and to a second input to the differential output amplifier through the third switch;

the common connection of the differential outputs of the first and second differential amplifiers being connectable to the differential inputs of the second differential amplifier by the fifth switch.

12. The amplifier of claim 11 wherein the output amplifier is a multiple stage amplifier.

13. The circuit of claim 11 further comprising a third amplifier having differential inputs coupled to the differential inputs of the amplifier system and an output coupled to the output amplifier.

14. The circuit of claim 11 wherein the third switches are all closed at the same time, but not when the fourth and fifth switches are closed, the fourth switches are all closed at the same time, but not when any of the third and fifth switches are closed, and the fifth switches are all closed at the same time, but not when any of the third or fourth switches are closed, whereby the switch operation is nonoverlapping, the fifth switches being closed at the first frequency with a duty cycle of less than 50%, the third switches being closed at a second frequency with a duty cycle of approximately 50%, except as interrupted for the closure of the fifth switches, and the fourth switches being closed at the second frequency with a duty cycle of approximately 50%, except as interrupted for the closure of the fifth switches.

15. The amplifier of claim 14 wherein the fifth switches are closed with a duty cycle of not more 25%.

16. The amplifier of claim 14 wherein the output amplifier is a multiple stage amplifier.

17. The circuit of claim 14 further having third and fourth differential inputs of the amplifier system forming a second differential input port, and further comprising:

a third differential amplifier having first and second differential inputs;

the third differential input of the amplifier system being connectable to the first differential input of the third differential amplifier by third and fifth switches, and to the second differential input of the third differential amplifier by the fourth and fifth switches;

the fourth differential input of the amplifier system being connectable to the first differential input of the third differential amplifier by the fourth switch and to the second differential input of the third differential amplifier by the third switch;

differential outputs of the third differential amplifier being coupled in common with the differential outputs of the first and second differential amplifiers.

18. The circuit of claim 17 further comprising fourth and fifth differential amplifiers, the fourth differential amplifier having differential inputs coupled to the first and second differential inputs of the amplifier system and an output coupled to the output amplifier, and the fifth differential amplifier having differential inputs coupled to the third and fourth differential inputs of the amplifier system and an output coupled to the output amplifier.

19. The circuit of claim 14 further comprising:

a timing circuit for providing three output timing signals for controlling the timing of the third, fourth and fifth switches respectively, the output timing signals having first and second states and being nonoverlapping in the second state, the three output timing signals being provided from three input signals of first and second states, any of which input signals may overlap in the second state, comprising;

logic coupled to delay the change of a first output timing signal to the second state response to a change of the first input signal to the second state until after both second and third output signals are in the first state;

logic coupled to delay the change of a second output timing signal to the second state response to a change of the second input signal to the second state until after both first and third output signals are in the first state; and

,

logic coupled to delay the change of a third output timing signal to the second state response to a change of the third input signal to the second state until after both first and second output signals are in the first state.

20. The circuit of claim 19 further comprising:

switch drive circuits for driving the third, fourth and fifth switches on the first and second differential inputs to the amplifier system to control their on and off states, respectively, each drive circuit being responsive to a respective output timing signal of the timing circuit, to control the on and off states of the third, fourth and fifth switches, respectively;

circuitry for connecting a first lead of a capacitor to a power supply voltage, a second capacitor lead to a circuit ground and holding the respective switch in the off state when the respective output timing signal is its first state; and

,

circuitry for connecting the second lead of the capacitor to a voltage responsive to a common mode voltage of the first and second differential inputs of the amplifier system and connecting the first capacitor lead to a control voltage for the respective switch when the circuit is clocked by a respective output timing signal;

whereby the control voltage for turning on the switches is approximately one power supply voltage above the common mode voltage of the first and second differential inputs of the amplifier system, independent of what the common mode voltage is.

21. A method of operating a chopper stabilized first amplifier, the chopper stabilized first amplifier having an auto-zeroing capability comprising:

operating the chopper stabilization at a first frequency; and

,

operating the auto-zeroing at a second frequency;

the ratio of the frequencies being two to one;

the second frequency being twice the first frequency and having a duty cycle of less than one half.

22. A method of operating a chopper stabilized first amplifier, the chopper stabilized first amplifier having an auto-zeroing capability comprising:

operating the chopper stabilization at a first frequency; and

,

operating the auto-zeroing at a second frequency;

the ratio of the frequencies being two to one;

the second frequency having a duty cycle of not more than one-quarter.

23. A method of operating a chopper stabilized first amplifier, the chopper stabilized first amplifier having an auto-zeroing capability comprising:

operating the chopper stabilization at a first frequency; and

,

operating the auto-zeroing at a second frequency;

the ratio of the frequencies being two to one;

after each cycle of the chopper stabilization of the first amplifier, chopper stabilizing a second amplifier using the same choppers;

auto-zeroing the second amplifier while the first amplifier is being chopper stabilized; and

,

auto-zeroing the first amplifier while the second amplifier is being chopper stabilized;

the outputs of the first and second amplifiers being connected in common.

24. A method of operating a chopper stabilized first amplifier, the chopper stabilized first amplifier having an auto-zeroing capability wherein the chopper stabilized first amplifier has first, second and third pluralities of open and closed switches, the first and second switches being coupled as input and output chopper switches and the third switches being coupled as auto-zero switches, wherein the first switches are all closed at the same time, but not when the second and third switches are closed, the second switches are all closed at the same time, but not when any of the first and third switches are closed, and the third switches are all closed at the same time, but not when the first or second switches are closed, whereby the switch operation is nonoverlapping, the third switches being closed at a first frequency with a duty cycle of less than 50%, the first switches being closed at a second frequency equal to one half the first frequency with a duty cycle of approximately 50%, except as interrupted for the closure of the third switches, and the second switches being closed at the second frequency with a duty cycle of approximately 50%, except as interrupted for the closure of the third switches;

operating the first and second switches at a first frequency; and

,

operating the third switches at a second frequency;

the ratio of the frequencies being two to one.

25. The method of claim 24 wherein the third switches are closed with a duty cycle of not more 25%.

26. The method of claim 25 wherein the output amplifier is a multiple stage amplifier.

27. The method of claim 24 wherein the first amplifier has first and second differential inputs and further comprising:

controlling, responsive to a clocking signal, the on and off states of switches controlling the connection of the first and second differential inputs to differential amplifier system inputs and to themselves, the differential amplifier system inputs having a common mode voltage, comprising, for each pair of switches;

connecting a first lead of a capacitor to a power supply voltage, a second capacitor lead to a circuit ground and holding the switches in the off state when the switch control circuit is not being clocked by one of a first, second or third timing signal; and

,

connecting the second lead of the capacitor to a voltage responsive to the common mode voltage and connecting the first capacitor lead to a control voltage when the circuit is clocked by the respective first, second or third timing signal;

whereby the control voltage for turning on the switches is approximately one power supply voltage above the common mode voltage, independent of what the common mode voltage is.

28. The method of claim 27 further comprising:

providing the first, second and third timing signals, each having first and second states corresponding to switch on and off states, the three timing signals being nonoverlapping in the first state from three input signals of first and second states, any two of which may overlap in the first state by;

delaying the change of the first timing signal to the first state response to a change of the first input signal to the first state until after both the second and the third timing signals are in the second state;

delaying the change of the second timing signal to the first state response to a change of the second input signal to the first state until after both the first and the third output signals are in the second state; and

,

delaying the change of the third timing signal to the first state response to a change of the third input signal to the first state until after both the first and the second output signals are in the second state.