Method for making high-performance RF integrated circuits

• US 7,973,629 B2
• Filed: 10/31/2007
• Issued: 07/05/2011
• Est. Priority Date: 09/04/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan
• Primary Examiner(s): NGUYEN, TUYEN T
• Application Number:
  US11/930,664
• Publication Number:
  US 20080054398A1
• Time in Patent Office: 1,343 Days
• Field of Search: 336/65, 336/200, 336206-208, 336/232, 257/531, 257758-759, 438113-114
• US Class Current: 336/200
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/12044 OLED
• CPC Class Codes: H01L 2924/1423 Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A new method and structure is provided for the creation of a semiconductor inductor. Under the first embodiment of the invention, a semiconductor substrate is provided with a scribe line in a passive surface region and active circuits surrounding the passive region. At least one bond pad is created on the passive surface of the substrate close to and on each side of the scribe line. A layer of insulation is deposited, a layer of dielectric is deposited over the layer of insulation, at least one bond pad is provided on the surface of the layer of dielectric on each side of the scribe line. At least one inductor is created on each side of the scribe line on the surface of the layer of dielectric. A layer of passivation is deposited over the layer of dielectric. The substrate is attached to a glass panel by interfacing the surface of the layer of passivation with the glass panel. The substrate is sawed from the backside of the substrate in alignment with the scribe line. The silicon that remains in place in the passive surface of the substrate underneath the scribe lines is removed by etching, the glass panel is separated along the scribe line. Under the second embodiment of the invention, the inductor is created on the surface of a thick layer of polymer that is deposited over the layer of passivation.

Claims

1. A semiconductor device comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect structure over said insulating layer and said active-surface region;

a second interconnect structure over said first interconnect structure and said active-surface region;

a dielectric layer between said first and second interconnect structures;

a passivation layer over said dielectric layer, said first and second interconnect structures, and said active-surface region;

a polymer layer over said passivation layer and said active-surface region, wherein a portion of said polymer layer extends in a horizontal direction beyond a boundary of said active-surface region; and

an inductor over said portion of said polymer layer, wherein there is no active device vertically under said inductor and said portion of said polymer layer.

2. The semiconductor device of claim 1, wherein said inductor is connected to said second interconnect structure.

3. The semiconductor device of claim 1, wherein said polymer layer comprises polyimide.

4. The semiconductor device of claim 1, wherein said polymer layer comprises benzocyclobutene (BCB).

5. The semiconductor device of claim 1 further comprising an interconnect line over said polymer layer, wherein said interconnect line is connected to said second interconnect structure through an opening in said polymer layer.

6. The semiconductor device of claim 1 further comprising a bond pad connected to said inductor, wherein said bond pad is configured to be connected to a surrounding circuit.

7. The semiconductor device of claim 1, wherein said polymer layer contacts said passivation layer.

8. The semiconductor device of claim 1, wherein said passivation layer comprises a nitride.

9. The semiconductor device of claim 1, wherein said inductor comprises a copper interconnect.

10. The semiconductor device of claim 1, wherein said inductor comprises an aluminum interconnect.

11. The semiconductor device of claim 1, wherein said passivation layer comprises an oxide.

12. A semiconductor device comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect structure over said insulating layer and said active-surface region;

a second interconnect structure over said first interconnect structure and said active-surface region;

a dielectric layer between said first and second interconnect structures;

a passivation layer over said dielectric layer, said first and second interconnect structures, and said active-surface region, wherein a portion of said passivation layer extends in a horizontal direction beyond a boundary of said active-surface region, wherein said passivation layer comprises a nitride; and

an inductor over said portion of said passivation layer, wherein there is no active device vertically under said inductor and said portion of said passivation layer.

13. The semiconductor device of claim 12 further comprising a polymer layer over said passivation layer and said active-surface region.

14. The semiconductor device of claim 13, wherein said polymer layer comprises polyimide.

15. The semiconductor device of claim 12 further comprising an interconnect line over said passivation layer, wherein said interconnect line is connected to said second interconnect structure through an opening in said passivation layer.

16. The semiconductor device of claim 12 further comprising a bond pad connected to said inductor, wherein said bond pad is configured to be connected to a surrounding circuit.

17. The semiconductor device of claim 12, wherein said inductor comprises a copper interconnect.

18. The semiconductor device of claim 12, wherein said inductor comprises an aluminum interconnect.

19. The semiconductor device of claim 12, wherein said nitride comprises silicon nitride.

20. The semiconductor device of claim 12, wherein said passivation layer further comprises an oxide.

21. A semiconductor device comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect structure over said insulating layer and said active-surface region;

a second interconnect structure over said first interconnect structure and said active-surface region;

a dielectric layer between said first and second interconnect structures, wherein a portion of said dielectric layer extends in a horizontal direction beyond a boundary of said active-surface region; and

an inductor over said portion of said dielectric layer, wherein there is no active device vertically under said inductor and said portion of said dielectric layer, wherein said inductor comprises a damascene copper interconnect.

22. The semiconductor device of claim 21 further comprising a polymer layer over said active-surface region, said first and second interconnect structures and said dielectric layer, wherein said inductor is further over said polymer layer.

23. The semiconductor device of claim 22, wherein said polymer layer comprises benzocyclobutene (BCB).

24. The semiconductor device of claim 22, wherein said polymer layer comprises polyimide.

25. The semiconductor device of claim 21 further comprising a passivation layer over said active-surface region, said first and second interconnect structures and said dielectric layer, wherein said passivation layer comprises a nitride, wherein said inductor is further over said passivation layer.

26. The semiconductor device of claim 21, wherein said dielectric layer comprises a nitride.

27. The semiconductor device of claim 21, wherein said dielectric layer comprises an oxide.

28. The semiconductor device of claim 21, wherein said dielectric layer comprises an oxynitride.

29. A semiconductor device comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect structure over said insulating layer;

a second interconnect structure over said first interconnect structure;

a dielectric layer between said first and second interconnect structures, wherein a portion of said dielectric layer extends in a horizontal direction beyond a boundary of said active-surface region;

an inductor over said portion of said dielectric layer, wherein there is no active device vertically under said inductor and said portion of said dielectric layer, wherein said inductor comprises a damascene copper interconnect; and

a passivation layer over said dielectric layer, said first and second interconnect structures, and said inductor, wherein said passivation layer comprises a nitride.

30. The semiconductor device of claim 29 further comprising a bond pad connected to said inductor, wherein said bond pad is configured to be connected to a surrounding circuit.

31. The semiconductor device of claim 29, wherein said nitride comprises silicon nitride.

32. The semiconductor device of claim 29, wherein said passivation layer further comprises an oxide.

33. A circuit component comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect line over said insulating layer and said active-surface region;

a dielectric layer over said insulating layer, said active-surface region and said first interconnect line;

a bond pad at a bottom of said dielectric layer, wherein said bond pad comprises a portion not vertically over said silicon substrate and is configured to be connected to a surrounding circuit;

a second interconnect line at a top of said dielectric layer and over said active-surface region;

a via in said dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via;

a passivation layer over said dielectric layer, said first and second interconnect lines and said bond pad;

a glass substrate over said passivation layer; and

an adhesive layer between said glass substrate and said passivation layer.

34. The circuit component of claim 33, wherein said passivation layer comprises a nitride.

35. The circuit component of claim 33, wherein a portion of said dielectric layer extends in a horizontal direction beyond a boundary of said active-surface region, further comprising an inductor over said portion of said dielectric layer, wherein there is no active device vertically under said inductor and said portion of said dielectric layer.

36. The circuit component of claim 33, wherein said passivation layer comprises an oxide.

37. The circuit component of claim 33, wherein said first interconnect line comprises a damascene copper interconnect.

38. The circuit component of claim 33, wherein said first interconnect line comprises an aluminum interconnect.

39. A circuit component comprising:

a silicon substrate having an active-surface region;

multiple active devices in or on said active-surface region;

an insulating layer over said active-surface region;

a first interconnect line over said insulating layer and said active-surface region;

a dielectric layer over said first interconnect line and said insulating layer, wherein said dielectric layer comprises a first portion vertically over said silicon substrate and a second portion not vertically over said silicon substrate, wherein said dielectric layer comprises an oxide;

a second interconnect line over said dielectric layer, said first interconnect line and said active-surface region;

a via in said dielectric layer and between said first and second interconnect lines, wherein said first interconnect line is connected to said second interconnect line through said via;

a passivation layer over said dielectric layer and said first and second interconnect lines, wherein said passivation layer comprises a first portion vertically over said silicon substrate, and a second portion vertically over said second portion of said dielectric layer and not vertically over said silicon substrate, wherein said passivation layer comprises a nitride; and

a third interconnect line over said passivation layer.

40. The circuit component of claim 39, wherein said passivation layer further comprises an oxide.

41. The circuit component of claim 39 further comprising a passive device over said dielectric layer.

42. The circuit component of claim 39 further comprising an inductor over said second portion of said dielectric layer.

43. The circuit component of claim 39, wherein said first interconnect line comprises a damascene copper interconnect.

44. The circuit component of claim 39, wherein said first interconnect line comprises an aluminum interconnect.

45. The circuit component of claim 39 further comprising a polymer layer over said third interconnect line.

46. The circuit component of claim 39 further comprising a polymer layer over said passivation layer, wherein said third interconnect line is further on said polymer layer.

47. The circuit component of claim 39, wherein said nitride comprises silicon nitride.