High intrascene dynamic range NTSC and PAL imager

• US 7,973,842 B2
• Filed: 04/14/2008
• Issued: 07/05/2011
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Barna, Sandor L., Subbotin, Igor, Kaplinsky, Michael, Cho, Kwang-Bo, Slayton, Gary E.
• Primary Examiner(s): Tran; Nhan T
• Assistant Examiner(s): Yoder, III; Chriss S
• Application Number:
  US12/081,302
• Publication Number:
  US 20080218621A1
• Time in Patent Office: 1,177 Days
• Field of Search: 348/257, 348/395, 348/396, 348/304, 348/305, 348/308, 348/295, 348/296, 257/291, 257/292
• US Class Current: 348/296
• CPC Class Codes: H04N 23/70 Circuitry for compensating brightness variation in the scene
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

The invention provides a new method and apparatus for NTSC and PAL image sensors which employs fusion of adjacent row pixel charge samples to generate image data for a row. A variety of fusion schemes are possible for fusing the pixel signals from the adjacent rows. The rows of pixels are scanned so that each scan takes an odd row signal sample and, in some cases, an adjacent even row signal sample when specified conditions are met. One sampled row of the two adjacent rows integrate an image with a first integration period while the other adjacent row integrates an image with a second integration period.

Claims

1. An imager comprising:

a first pixel circuit in a first pixel row for outputting at least a first pixel image signal accumulated during a first integration period;

a second pixel circuit in a pixel row different from the first pixel row for outputting at least a second pixel image signal accumulated during a second integration period, which is shorter than said first integration period; and

a sample and hold circuit configured to selectively acquire at least one of said first and second pixel image signals and perform a comparison of said first pixel image signal to a threshold signal value, and to output a pixel output signal generated from at least one of said first and second pixel image signals based on the result of said comparison.

2. The imager of claim 1, wherein said pixel output signal is one of a combination of said first and second pixel signals or a selection of one of said first and second pixel image signals.

3. The imager of claim 2, wherein said pixel output signal comprises a combination of said first and second pixel signals when said first pixel image signal is greater than said threshold signal value.

4. The imager of claim 3, wherein said combination of said first and second pixel signals is an average of said first and second pixel signals.

5. The imager of claim 2, wherein said pixel output signal comprises said first pixel image signal when said first pixel image signal is greater than said threshold signal value.

6. The imager of claim 2, wherein said pixel output signal comprises said second pixel image signal when said first pixel image signal is less than said threshold signal value.

7. The imager of claim 1, wherein said threshold signal value is approximately equal to a saturation value for a pixel in either said first pixel row or said pixel row different from said first pixel row.

8. A readout system comprising:

at least one sample and hold circuit configured to sample a first pixel signal from a first selected row of pixels having a first integration period, said sample and hold circuit further configured to selectively sample a second pixel signal from a second adjacent selected row of pixels, which has a second integration period shorter than said first integration period;

a switching circuit coupled to said at least one sample and hold circuit and being configured to control sampling of said first and second pixel signals; and

a comparator configured to determine if a sampled first pixel signal exceeds a threshold signal value,

said switching circuit being further configured to operate said at least one sample and hold circuit to sample said first pixel signal and to provide a first output signal if said comparator determines that said threshold is exceeded by said sampled first pixel signal, and to operate said at least one sample and hold circuit to sample and hold said second pixel signal and to provide a second output signal when said threshold is not exceeded,

wherein said first output signal is different from said second output signal.

9. The readout system of claim 8, wherein said first output signal is a combination of said first and second pixel signals.

10. The readout system of claim 9, wherein said combination of said first and said second pixel signals is an average of said first and second pixel signals.

11. The readout system of claim 8, wherein said first output signal is said first pixel signal.

12. The readout system of claim 8, wherein said second output signal is said second pixel signal.

13. The readout system of claim 8, wherein said at least one sample and hold circuit comprises a plurality of sample and hold circuits.

14. The readout system of claim 13, wherein each of said plurality of sample and hold circuits is coupled to a column line.

15. The readout system of claim 8, wherein a pixel array comprises a plurality of sets of said first row of pixels with a first integration period and said second adjacent row of pixels with a shorter integration period.

16. The readout system of claim 8, wherein said switching circuit is configured to control sampling of said pixel rows in a pixel array such that said sampling begins at a first row on one end of the pixel array and is repeated for each of a said first row and said second adjacent row set, said sampling proceeding in the direction of the opposite end of said pixel array where said first row is located.

17. The readout system of claim 8, further comprising a digital image processing unit, said unit comprising a gamma table lookup for conversion of an output signal from one display output signal to another.

18. The readout system of claim 8, further comprising a flag storage circuit configured to store a flag, wherein said flag is set to a first value if said comparator determines said threshold is exceeded and said flag is set to a second value if said comparator determines said threshold is not exceeded said flag being used to control said at least one sample and hold circuit.

19. The readout system of claim 18, further comprising an amplifier for output of said at least one sample and hold circuit and a digital image processing circuit coupled to said amplifier, wherein said digital image processing circuit performs additional image processing based on the status of said flag.

20. The readout system of claim 8, wherein said threshold value is a signal that corresponds to a pixel saturation signal.