Transmission gate-based spin-transfer torque memory unit
First Claim
1. A memory unit comprising:
- a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and
a NMOS transistor in parallel electrical connection with a PMOS transistor, the NOMS transistor and the PMOS transistor electrically connected with the source line and the magnetic tunnel junction data cell, the PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
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Abstract
A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
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Citations
20 Claims
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1. A memory unit comprising:
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a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and a NMOS transistor in parallel electrical connection with a PMOS transistor, the NOMS transistor and the PMOS transistor electrically connected with the source line and the magnetic tunnel junction data cell, the PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A spin-transfer torque memory unit comprising:
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a bit line; a source line; a magnetic tunnel junction data cell electrically coupled to the bit line and the source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and a transmission gate electrically between the source line and the magnetic tunnel junction data cell, the transmission gate comprising; a NMOS transistor in parallel electrical connection with a PMOS transistor, the PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and not the NMOS transistor and a second write current in a second direction flows through the NMOS transistor and not the PMOS transistor. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A spin-transfer torque memory unit comprising:
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a bit line; a source line; a magnetic tunnel junction data cell comprising a ferromagnetic free layer and a ferromagnetic reference layer separated by a oxide barrier layer, the magnetic tunnel junction data cell electrically coupled to the bit line and the source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and a transmission gate electrically between the source line and the magnetic tunnel junction data cell, the transmission gate comprising; a NMOS transistor in parallel electrical connection with a PMOS transistor, the NMOS transistor comprising a NMOS gate electrode and the PMOS transistor comprising a PMOS gate electrode; a first word line is electrically coupled to the NMOS gate electrode; and a second word line is electrically coupled to the PMOS gate electrode, the second word line being electrically isolated from the first word line; wherein, the spin-transfer torque memory unit is configured so that a first write current in a first direction flows through the PMOS transistor and not the NMOS transistor and a second write current in a second direction flows through the NMOS transistor and not the PMOS transistor. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification