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Transmission gate-based spin-transfer torque memory unit

  • US 7,974,119 B2
  • Filed: 07/10/2008
  • Issued: 07/05/2011
  • Est. Priority Date: 07/10/2008
  • Status: Expired due to Fees
First Claim
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1. A memory unit comprising:

  • a magnetic tunnel junction data cell electrically coupled to a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

    a NMOS transistor in parallel electrical connection with a PMOS transistor, the NOMS transistor and the PMOS transistor electrically connected with the source line and the magnetic tunnel junction data cell, the PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

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