Operation methods for memory cell and array for reducing punch through leakage
First Claim
1. An integrated circuit comprising:
- a plurality of memory cells on a substrate; and
a circuit unit performing steps comprising;
selecting a first memory cell, the first memory cell comprising a first doped region, a second doped region, a first channel region therebetween, a first charge storage member overlying the first channel region, and a first control gate overlying the first charge storage member;
selecting a third doped region, the third doped region being separated from the second doped region by at least a second channel region, a second control gate overlying the second channel region;
applying a bias arrangement to program the first memory cell, including;
applying a substrate voltage to the substrate;
applying a first voltage to the first doped region;
applying a second voltage to the third doped region;
applying a third voltage to the first control gate and the second control gate; and
floating the second doped region.
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Accused Products
Abstract
A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.
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Citations
28 Claims
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1. An integrated circuit comprising:
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a plurality of memory cells on a substrate; and a circuit unit performing steps comprising; selecting a first memory cell, the first memory cell comprising a first doped region, a second doped region, a first channel region therebetween, a first charge storage member overlying the first channel region, and a first control gate overlying the first charge storage member; selecting a third doped region, the third doped region being separated from the second doped region by at least a second channel region, a second control gate overlying the second channel region; applying a bias arrangement to program the first memory cell, including; applying a substrate voltage to the substrate; applying a first voltage to the first doped region; applying a second voltage to the third doped region; applying a third voltage to the first control gate and the second control gate; and floating the second doped region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of operating a memory array on a substrate having a plurality of memory cells, the method comprising:
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providing a circuit performing steps comprising; selecting a first memory cell, the first memory cell comprising a first doped region, a second doped region, a first channel region therebetween, a first charge storage member overlying the first channel region, and a first control gate overlying the first charge storage member; selecting a third doped region, the third doped region being separated from the second doped region by at least a second channel region, a second charge storage member overlying the second channel region, and a second control gate overlying the second channel region; and applying a bias arrangement to program the first memory cell, including; applying a substrate voltage to the substrate; applying a first voltage to the first doped region; applying a second voltage to the third doped region; applying a third voltage to the first control gate and the second control gate; and floating the second doped region. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification