Operation methods for memory cell and array for reducing punch through leakage

• US 7,974,127 B2
• Filed: 11/04/2008
• Issued: 07/05/2011
• Est. Priority Date: 11/06/2007
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Tsai, Wen-Jer, Huang, Jyun-Siang, Ou, Tien-Fan, Chong, Lit-Ho
• Primary Examiner(s): Phan; Trong
• Application Number:
  US12/264,886
• Publication Number:
  US 20090116286A1
• Time in Patent Office: 973 Days
• Field of Search: 365/185.03, 365/185.05, 365/185.16, 365/185.17, 365/185.18, 365/185.24, 365/185.26, 365/185.27, 365/185.28, 365/185.29, 365/185.33
• US Class Current: 365/185.16
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells.

Claims

1. An integrated circuit comprising:

a plurality of memory cells on a substrate; and

a circuit unit performing steps comprising;

selecting a first memory cell, the first memory cell comprising a first doped region, a second doped region, a first channel region therebetween, a first charge storage member overlying the first channel region, and a first control gate overlying the first charge storage member;

selecting a third doped region, the third doped region being separated from the second doped region by at least a second channel region, a second control gate overlying the second channel region;

applying a bias arrangement to program the first memory cell, including;

applying a substrate voltage to the substrate;

applying a first voltage to the first doped region;

applying a second voltage to the third doped region;

applying a third voltage to the first control gate and the second control gate; and

floating the second doped region.

2. The integrated circuit of claim 1, wherein the bias arrangement turns on the first channel region and the second channel region and injects a first type of charges to the first charge storage member of the first memory cell.

3. The integrated circuit of claim 1, wherein the bias arrangement injects a first type of charges to the first charge storage member of the first memory cell and is insufficient to turn on the first channel region.

4. The integrated circuit of claim 3, wherein the steps further comprise:

selecting a second memory cell adjacent to the first memory cell, the second memory cell comprising the first doped region, a fourth doped region, a third channel region therebetween, a second charge storage member overlying the third channel region, a third control gate overlying the third channel region; and

applying a fourth voltage to the fourth doped region, such that the second charge storage member is free from being programmed, wherein the fourth voltage is not more than the first voltage.

5. The integrated circuit of claim 1, wherein the third doped region is separated from the second doped region by two or more channel regions, the bias arrangement further comprising:

applying the third voltage to the control gates overlying each of the two or more channel regions to turn on each of the two or more channel regions; and

floating the doped regions between each adjacent pair of the two or more channel regions.

6. The integrated circuit of claim 1, wherein each of the plurality of memory cells is capable of holding multiple bits of information, the bias arrangement further comprising programming the memory cell until a threshold voltage of the memory cell is within a predetermined range of a threshold voltage target.

7. The integrated circuit of claim 1, wherein the steps further comprise reading the first memory cell by including:

applying a fourth voltage to the first doped region;

applying a fifth voltage to the second doped region, the fifth voltage is less than the fourth voltage; and

applying a sixth voltage to the first control gate;

whereby a current served as an indication of an amount of injected charges at least in a portion of the first charge storage member is provided at the first doped region.

8. The integrated circuit of claim 1, wherein the steps further comprise reading the first memory cell by including:

applying a fourth voltage to the first doped region;

applying a fifth voltage to the second doped region, wherein the fourth voltage is less than the fifth voltage; and

applying a sixth voltage to the first control gate;

whereby a current served as an indication of an amount of injected charges at least in a portion of the first charge storage member is provided at the second doped region.

9. The integrated circuit of claim 2, wherein the step further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate;

applying a fifth voltage to the first control gate; and

applying a sixth voltage to the first doped region, whereby a second type of charges are injected to the first charge storage member to erase the first memory cell.

10. The integrated circuit of claim 2, wherein the step further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby the first type of charges are removed from the first charge storage member.

11. The integrated circuit of claim 2, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby a second type of charges are injected from the substrate to the first charge storage member.

12. The integrated circuit of claim 3, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby a second type of charges are injected from the first gate to the first charge storage member of the first memory.

13. The integrated circuit of claim 3, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, and applying a sixth voltage to one of the first doped region and the second doped region, whereby a second type of charges are injected from the substrate to the first charge storage member of the first memory.

14. The integrated circuit of claim 3, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, and applying a sixth voltage to one of the first doped region and the second doped region, whereby the first type of charges are removed from the first charge storage member of the first memory cell.

15. A method of operating a memory array on a substrate having a plurality of memory cells, the method comprising:

providing a circuit performing steps comprising;

selecting a first memory cell, the first memory cell comprising a first doped region, a second doped region, a first channel region therebetween, a first charge storage member overlying the first channel region, and a first control gate overlying the first charge storage member;

selecting a third doped region, the third doped region being separated from the second doped region by at least a second channel region, a second charge storage member overlying the second channel region, and a second control gate overlying the second channel region; and

applying a bias arrangement to program the first memory cell, including;

applying a substrate voltage to the substrate;

applying a first voltage to the first doped region;

applying a second voltage to the third doped region;

applying a third voltage to the first control gate and the second control gate; and

floating the second doped region.

16. The method of claim 15, wherein the bias arrangement turns on the first channel region and the second channel region and injects a first type of charges to the first charge storage member of the first memory cell.

17. The method of claim 15, wherein the bias arrangement injects a first type of charges to the first charge storage member of the first memory cell and is insufficient to turn on the first channel region.

18. The method of claim 17, wherein the steps further comprise:

selecting a second memory cell adjacent to the first memory cell, the second memory cell comprising the first doped region, a fourth doped region, a third channel region therebetween, a third charge storage member overlying the third channel region, a third control gate overlying the third channel region, wherein the third control gate couples the second control gate and the first control gate; and

applying a fourth voltage to the fourth doped region, such that the third charge storage member is free from being programmed, wherein the fourth voltage is not more than the first voltage.

19. The method of claim 15, wherein the third doped region is separated from the second doped region by two or more channel regions, and wherein the bias arrangement further comprising:

applying the third voltage to the control gates overlying each of the two or more channel regions to turn on each of the two or more channel regions; and

floating the doped regions between each adjacent pair of the two or more channel regions.

20. The method of claim 15, wherein each of the plurality of memory cells is capable of holding multiple bits of information, the bias arrangement further comprising programming the memory cell until a threshold voltage of the memory cell is within a predetermined range of a threshold voltage target.

21. The method of claim 15, wherein the steps further comprise reading the first memory cell by including:

applying a fourth voltage to the first doped region;

applying a fifth voltage to the second doped region, the fifth voltage is less than the fourth voltage; and

applying a sixth voltage to the first control gate;

whereby a current served as an indication of an amount of injected charges at least in a portion of the first charge storage member is provided at the first doped region.

22. The method of claim 15, wherein the steps further comprise reading the first memory cell by including:

applying a fourth voltage to the first doped region;

applying a fifth voltage to the second doped region, wherein the fourth voltage is less than the fifth voltage; and

applying a sixth voltage to the first control gate;

whereby a current served as an indication of an amount of injected charges at least in a portion of the first charge storage member is provided at the second doped region.

23. The method of claim 16, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate;

applying a fifth voltage to the first control gate; and

applying a sixth voltage to the first doped region, whereby a second type of charges are injected to the first charge storage member to erase the first memory cell.

24. The method of claim 16, wherein the steps further comprises erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby the first type of charges are removed from the first charge storage member.

25. The method of claim 16, wherein the steps further comprise erasing the first memory cell including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby a second type of charges are injected from the substrate to the first charge storage member.

26. The method of claim 17, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, whereby a second type of charges are injected from the first gate to the first charge storage member of the first memory.

27. The method of claim 17, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, and applying a sixth voltage to one of the first doped region and the second doped region, whereby a second type of charges are injected from the substrate to the first charge storage member of the first memory.

28. The method of claim 17, wherein the steps further comprise erasing the first memory cell by including:

applying a fourth voltage to the substrate; and

applying a fifth voltage to the first control gate, and applying a sixth voltage to one of the first doped region and the second doped region, whereby the first type of charges are removed from the first charge storage member of the first memory cell.