Non-volatile semiconductor memory device and erasing method thereof

• US 7,974,135 B2
• Filed: 03/24/2009
• Issued: 07/05/2011
• Est. Priority Date: 06/10/2008
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Dai
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/409,676
• Publication Number:
  US 20090303799A1
• Time in Patent Office: 833 Days
• Field of Search: 365/185.17, 365/185.2, 365/185.22, 365/185.29, 365/185.33
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells

Abstract

A non-volatile semiconductor memory device including a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit.

Claims

1. A non-volatile semiconductor memory device comprising a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein

the memory device has an erase-verify mode for verifying an erase state of the memory cells in the NAND cell unit, the erase-verify mode including two verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit, and wherein

the two verify-read operations in the erase-verify mode are as follows:

a first verify-read operation is for verifying the erase state of all memory cells in such a way as to detect whether the bit line is charged up or not under the condition that (a) all word lines coupled to control gates of the memory cells in the NAND cell unit are applied with verify-read voltage, (b) the source line is applied with bit line charging voltage, (c) the second select gate transistor is turned on, and (d) the first select gate transistor is turned on later than the second select gate transistor; and

a second verify-read operation is for verifying the erase state of the memory cell disposed adjacent to the first select gate transistor after the first verify-read operation in such a way as to temporally turn off the second select gate transistor, and make the bit line discharged, and then turn on again the second select gate transistor, thereby detecting whether the bit line is charged up or not under the condition that (e) the bit line charging voltage applied to the source line and the verify-read voltage applied to the word lines are kept as it is, and (f) the first select gate transistor is kept on.

2. The non-volatile semiconductor memory device according to claim 1, wherein

in the second verify-read operation, some word lines corresponding to the memory cells excepting that disposed adjacent to the first select gate transistor are applied with a read pass voltage higher than the verify-read voltage.

3. The non-volatile semiconductor memory device according to claim 1, wherein

two memory cells disposed adjacent to the first and second select gate transistors in the NAND cell unit serve as dummy cells, which are not used for storing data.

4. The non-volatile semiconductor memory device according to claim 1, wherein

the erase-verify mode including the two verify-read operations is adapted only when the erase number is over a certain value while all memory cells in the NAND cell unit are erase-verified in a lump at remaining erase-verify times.

5. A method of erasing a non-volatile semiconductor memory device, which comprises a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, comprising:

erasing all memory cells in the NAND cell unit, and

erase-verifying the all memory cells with first and second verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit, wherein

the first verify-read operation is for verifying an erase state of the all memory cells in such a way as to detect whether the bit line is charged up or not under the condition that (a) all word lines coupled to control gates of the memory cells in the NAND cell unit are applied with verify-read voltage, (b) the source line is applied with bit line charging voltage, (c) the second select gate transistor is turned on, and (d) the first select gate transistor is turned on later than the second select gate transistor, and wherein

the second verify-read operation is for verifying the erase state of the memory cell disposed adjacent to the first select gate transistor following the first verify-read operation in such a way as to temporally turn off the second select gate transistor, and make the bit line discharged, and then turn on again the second select gate transistor, thereby detecting whether the bit line is charged up or not under the condition that (e) the bit line charging voltage applied to the source line and the verify-read voltage applied to the word lines are kept as it is, and (f) the first select gate transistor is kept on.

6. The method according to claim 5, wherein

in the second verify-read operation, some word lines corresponding to the memory cells excepting that disposed adjacent to the first select gate transistor are applied with a read pass voltage higher than the verify-read voltage.

7. The method according to claim 5, wherein

two memory cells disposed adjacent to the first and second select gate transistors in the NAND cell unit serve as dummy cells, which are not used for storing data.

8. The method according to claim 5, wherein

the erase-verifying procedure including the first and second verify-read operations is adapted only when the erase number is over a certain value while a conventional erase-verify procedure is adapted for verify-reading all memory cells in the NAND cell unit in a lump at remaining erase-verify times.

9. A method of erasing a non-volatile semiconductor memory device, which comprises a NAND cell unit with a plurality of electrically rewritable and non-volatile memory cells connected in series, one end thereof being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, comprising:

erasing all memory cells in the NAND cell unit;

judging whether a number of erase operations has reached a predetermined value or not;

erase-verifying the all memory cells in a lump with a conventional verify-reading procedure while the number of erase operations is not over the predetermined value; and

erase-verifying the all memory cells with first and second verify-read operations adapted according to cell ranges to be erase-verified in the NAND cell unit when the number of erase operations is over the predetermined value, wherein

the first verify-read operation is for verifying an erase state of the all memory cells in such a way as to detect whether the bit line is charged up or not under the condition that (a) all word lines coupled to the control gates of the memory cells in the NAND cell unit are applied with verify-read voltage, (b) the source line is applied with bit line charging voltage, (c) the second select gate transistor is turned on, and (d) the first select gate transistor is turned on later than the second select gate transistor, and wherein

the second verify-read operation is for verifying the erase state of the memory cell disposed adjacent to the first select gate transistor following the first verify-read operation in such a way as to temporally turn off the second select gate transistor, and make the bit line discharged, and then turn on again the second select gate transistor, thereby detecting whether the bit line is charged up or not under the condition that (e) the bit line charging voltage applied to the source line and the verify-read voltage applied to the word lines are kept as it is, and (f) the first select gate transistor is kept on.

10. The method according to claim 9, wherein

in the second verify-read operation, some word lines corresponding to the memory cells excepting that disposed adjacent to the first select gate transistor are applied with a read pass voltage higher than the verify-read voltage.

11. The method according to claim 9, wherein

two memory cells disposed adjacent to the first and second select gate transistors in the NAND cell unit serve as dummy cells, which are not used for storing data.