Wordline temperature compensation

• US 7,974,146 B2
• Filed: 12/19/2008
• Issued: 07/05/2011
• Est. Priority Date: 12/19/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Barkley, Gerald J
• Primary Examiner(s): Dinh; Son T
• Application Number:
  US12/339,935
• Publication Number:
  US 20100157672A1
• Time in Patent Office: 928 Days
• Field of Search: 365/230.06, 365/211, 365/189.05, 365/230.08, 365/240
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature compensated wordline signal(s) to the nonvolatile memory. The temperature compensated wordline signals change as the temperature dependent read window changes.

Claims

1. A system comprising:

a processor; and

a nonvolatile memory coupled to the processor, the nonvolatile memory having a floating gate transistor with a temperature dependent threshold voltage, and a temperature compensated wordline voltage supply circuit coupled to provide a wordline signal to the floating gate transistor, wherein the temperature compensated wordline voltage supply circuit includes a resistor with a temperature dependent resistance value, wherein the nonvolatile memory comprises a multi-level cell (MLC) memory, and the temperature compensated wordline voltage supply circuit comprises a first voltage reference circuit to pull-up the wordline signal to a first wordline voltage, and a second voltage reference circuit to pull-down the wordline signal to a second wordline voltage, and wherein the second voltage reference circuit includes a temperature compensated output circuit with a source follower transistor, a current source, and the resistor with the temperature dependent resistance value.

2. The system of claim 1 further comprising a communications transceiver coupled to the processor.

3. The system of claim 1 wherein the nonvolatile memory comprises a NOR flash memory.

4. A memory device comprising:

a nonvolatile memory cell including a floating gate transistor having a threshold voltage; and

a temperature compensated wordline voltage supply circuit to provide a wordline signal to the floating gate transistor, the temperature compensated wordline voltage supply circuit including;

a temperature compensation resistor having a positive temperature coefficient;

a current source to source a substantially constant current to the temperature compensation resistor; and

a programmable flash cell, and the current source and the temperature compensation resistor are coupled in a feedback loop with the programmable flash cell.

5. The memory device of claim 4 wherein the temperature compensated wordline voltage supply circuit includes a pull-up open loop output circuit to provide the wordline signal.

6. The memory device of claim 4 wherein the temperature compensated wordline voltage supply circuit includes a pull-down output circuit to provide the wordline signal, wherein the temperature compensation resistor and the current source are included in the pull-down output circuit.

7. The memory device of claim 4 wherein the floating gate transistor forms a multilevel memory cell (MLC).

8. A voltage reference circuit comprising:

a first flash cell to receive a reference voltage and to produce a threshold voltage current;

a second flash cell having a threshold voltage programmed to be substantially equal to a desired output voltage of the voltage reference circuit, the second flash cell being coupled to the first flash cell through a current mirror to allow the threshold voltage current to flow as a drain current in the second flash cell;

a source follower feedback circuit including a first source follower transistor, a current source, and a temperature compensation resistor coupled between the current source and a drain node of the first source follower transistor, the first source follower transistor having a gate node coupled to a drain node of the second flash cell, and a gate node of the second flash cell coupled to a node common to the temperature compensation resistor and the current source; and

a source follower output circuit including a second source follower transistor with a gate node coupled in common with the gate node of the first source follower transistor.

9. The voltage reference circuit of claim 8 wherein the first and second source follower transistors are p-channel metal oxide semiconductor field effect transistors.

10. The memory device of claim 9 wherein the source follower output circuit comprises a pull-up circuit.

11. The memory device of claim 8 wherein the temperature compensation resistor has a positive temperature coefficient.

12. The voltage reference circuit of claim 11 wherein the current source sources a current through the temperature compensation resistor, and a voltage across the temperature compensation resistor changes with temperature to change the wordline voltage with temperature.