Linear phase detector and clock/data recovery circuit thereof

• US 7,974,375 B2
• Filed: 08/23/2007
• Issued: 07/05/2011
• Est. Priority Date: 08/24/2006
• Status: Active Grant

• Current Assignee: Korea University Industrial & Academic Collaboration Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Korea University Industrial & Academic Collaboration Foundation, Samsung Electronics Co. Ltd.
• Inventors: Lee, In-Ho, Kim, Chul-Woo, Yoon, Seok-Soo, Kwak, Young-Ho, Kim, Ki-Hong
• Primary Examiner(s): Burd; Kevin M
• Assistant Examiner(s): Perez; James M
• Application Number:
  US11/843,785
• Publication Number:
  US 20080049884A1
• Time in Patent Office: 1,412 Days
• Field of Search: 375/316, 375/354, 375359-360, 375369-371, 375373-376, 327/100, 327/141, 327/144, 327146-148, 327/152, 327155-157, 327/231, 327233-236, 327243-245
• US Class Current: 375/376
• CPC Class Codes: H03D 13/00 Circuits for comparing the phase or frequency of two mutually-independent oscillations measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump

Abstract

A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Claims

1. A linear phase detector comprising:

a data transition detector receiving data signals and configured to determine whether a transition is present in the received data signals;

an up/down pulse generator coupled to said data transition detector and receiving said data signals and a recovered clock signal, said up/down pulse generator generating up and down pulses that have pulse widths proportional to phase differences between transitions of the data signals and edges of the recovered clock signal; and

a multiplexer coupled to said data transition detector and said up/down pulse generator, said multiplexer receiving a selection signal from said transition detector and outputting up and down pulses at transitions of said data signals.

2. The linear phase detector as set forth in claim 1, wherein the up and down pulses are selectively output in accordance with a transition of the data.

3. The linear phase detector as set forth in claim 1, wherein the up and down pulses are output if a transition of the data is present.

4. The linear phase detector as set forth in claim 1, wherein the up and down pulses are interrupted to be output if a transition of the data is absent.

5. The linear phase detector as set forth in claim 1, wherein the up/down pulse generator is configured to add the same pulse width to the up and down pulses during fast data transmission.

6. A clock/data recovery circuit comprising:

a voltage-controlled oscillator configured to generate a recovered clock signal;

a phase detector configured to generate up and down pulses in response to received data signals and said recovered clock signal from said voltage-controlled oscillator, the phase detector further comprising;

a data transition detector receiving data signals and configured to determine whether a transition is present in the received data signals;

an up/down pulse generator coupled to said data transition detector and said received data signals and said recovered clock signal, said up/down pulse generator generating the up and down pulses that have pulse widths proportional to phase differences between transitions of the data signals and edges of the recovered clock signal; and

a multiplexer coupled to said data transition detector and said up/down pulse generator, said multiplexer receiving a selection signal from said transition detector and outputting up and down pulses at transitions of said data signals; and

a control circuit configured to control the voltage-controlled oscillator in response to the up and down pulses to synchronize an edge of the recovered clock signal with the center of the data signal,

wherein the recovered clock signal comprises multiphase clock signals, and the phase detector generates up and down pulses for each of the multiphase clock signals.

7. The clock/data recovery circuit as set forth in claim 6 wherein the up and down pulses have the same pulse width when an edge of the recovered clock signal is synchronized with the center of the data signal.

8. The clock/data recovery circuit as set forth in claim 6 wherein said phase detector is configured to output the up and down pulses if a transition in the data signals is present.

9. The clock/data recovery circuit as set forth in claim 6 wherein said phase detector is configured to interrupt the up and down pulses if a transition in the data signal is absent.

10. The clock/data recovery circuit as set forth in claim 6 wherein said phase detector is configured to add the same pulse width to the up and down pulses during data transmission at a particular frequency.

11. The clock/data recovery circuit as set forth in claim 6 wherein the control circuit comprises:

a charge pump generating a control voltage in response to the up and down pulses; and

a filter coupled to said charge pump and configured to output the control voltage to the voltage-controlled oscillator.