Methods of reducing interference including applying weights to provide correction signals and related systems
First Claim
Patent Images
1. A method of reducing interference in a satellite communications system, the method comprising:
- providing first and second feeder link signals;
applying a first weight to the second feeder link signal to provide a first correction signal;
combining the first correction signal with the first feeder link signal to provide a first interference reduced feeder link signal;
applying a second weight to the first feeder link signal to provide a second correction signal; and
combining the second correction signal with the second feeder link signal to provide a second interference reduced feeder link signal.
17 Assignments
0 Petitions
Accused Products
Abstract
Methods of reducing interference in a satellite communications system may include receiving a plurality of feeder link signals and time aligning the plurality of feeder link signals to provide time aligned feeder link signals. At least two of the time aligned feeder link signals may be combined to provide reduced interference of at least one of the feeder link signals. Related systems are also discussed.
-
Citations
22 Claims
-
1. A method of reducing interference in a satellite communications system, the method comprising:
-
providing first and second feeder link signals; applying a first weight to the second feeder link signal to provide a first correction signal; combining the first correction signal with the first feeder link signal to provide a first interference reduced feeder link signal; applying a second weight to the first feeder link signal to provide a second correction signal; and combining the second correction signal with the second feeder link signal to provide a second interference reduced feeder link signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A satellite communications system comprising:
a processor configured to apply a first weight to a second feeder link signal to provide a first error correction signal, and to combine the first error correction signal with a first feeder link signal to provide a first interference reduced feeder link signal, wherein the processor is further configured to apply a second weight to the first feeder link signal to provide a second error correction signal, and to combine the second error correction signal with the second feeder link signal to provide a second interference reduced feeder link signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
Specification