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Method for efficient I/O controller processor interconnect coupling supporting push-pull DMA read operations

  • US 7,975,090 B2
  • Filed: 07/07/2009
  • Issued: 07/05/2011
  • Est. Priority Date: 07/07/2009
  • Status: Expired due to Fees
First Claim
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1. A system for I/O controller-processor interconnect coupling supporting push-pull DMA operations, comprising:

  • a processor interconnect comprising a plurality of caches and memory subsystems;

    an I/O controller coupled with the processor interconnect comprising;

    a plurality of DMA read request queues;

    a DMA read slot pool comprising a plurality of DMA read slots, wherein the DMA read slot pool includes at least a scout slot operable to send a scout request to the processor interconnect inquiring a data origin of a request in said request queues and to notify the data origin to the expander logic in response to receiving a response to the inquiry from the processor interconnect;

    wherein the data origin includes one or more levels of cache memory, memory supporting pre-fetching, memory not supporting pre-fetching, or combinations thereof;

    and an expander logic determining a priority of requests in said request queues.

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