Processor cache management with software input via an intermediary

• US 7,975,107 B2
• Filed: 06/22/2007
• Issued: 07/05/2011
• Est. Priority Date: 06/22/2007
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Waters, Bradley M., Beckmann, Bradford
• Primary Examiner(s): Kim; Matt
• Assistant Examiner(s): Rossiter; Sean
• Application Number:
  US11/821,140
• Publication Number:
  US 20080320235A1
• Time in Patent Office: 1,474 Days
• Field of Search: 717/150, 717/151, 717/160
• US Class Current: 711/118
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning

Abstract

Software assists a processor subsystem in making cache replacement decisions by providing an intermediary with information regarding how instructions and/or data of a working set are expected to be used and accessed by the software. The intermediary uses this information along with its knowledge of system requirements, policy and the cache configuration to determine cache usage and management hints for the working sets. The cache usage and management hints are passed by the intermediary to the processor subsystem.

Claims

1. A method of cache management in a computer system, the method comprising:

receiving, from an upper layer of software of the computer system, an access behavior description at an intermediary between the upper layer of software and a processor subsystem of the computer system, the access behavior description comprising an indication of how items of a working set are going to be accessed by the upper layer of software when the upper layer of software is executed by the processor subsystem;

determining, by the intermediary, a cache usage management hint based upon a cache configuration of the processor subsystem and the access behavior description specifying a stream access pattern, the cache usage management hint preventing items of the working set from being cached in caches larger than a smallest cache larger than a window corresponding to the stream access pattern; and

providing, by the intermediary, the cache usage management hint to the processor subsystem for consideration by the processor subsystem when performing cache management for at least one cache.

2. The method of claim 1 comprising:

storing the access behavior description and the cache usage management hint internally in the intermediary at a page level.

3. The method of claim 2, storing the access behavior description and the cache usage management hint comprising:

storing the access behavior description and the cache usage management hint in a page table maintained by an operating system of the computer system.

4. The method of claim 1, providing the cache usage management hint to the processor subsystem comprising:

providing the cache usage management hint to the processor subsystem as additional information in a translation lookaside buffer fill.

5. The method of claim 1 comprising:

storing the access behavior description and the cache usage management hint internally in the intermediary at a cache-line level.

6. The method claim 1, the intermediary comprising an operating system and receiving the access behavior description comprising:

receiving the access behavior description as additional information when requesting that the operating system allocate memory.

7. The method of claim 1, comprising:

determining the cache usage management hint based upon the access behavior description indicating items of the working set will be accessed by the upper layer of software once, the cache usage management hint specifying the items of the working set are to be stored in memory and not cache.

8. The method of claim 1, comprising:

determining the cache usage management hint based upon the window being larger than a next-to-largest cache, the cache usage management hint specifying a least recently used cache replacement policy.

9. A processor subsystem comprising:

at least one processor;

an intermediary configured to determine a cache usage management hint based upon a cache configuration of the processor subsystem and an access behavior description specifying a stream access pattern of how items of a working set are going to be accessed by an upper layer of software, the cache usage management hint preventing items of the working set from being cached in caches larger than a smallest cache larger than a window corresponding to the stream access pattern;

one or more caches configured to store items of working sets; and

a tracking component configured to track performance events within the processor subsystem.

10. The processor subsystem of claim 9, the tracking component configured to:

provide the upper layer of a software of a computer system with a cache eviction performance event comprising at least one of a physical address and a virtual address of a load or store instruction causing the cache eviction performance event, a timestamp of a cycle counter, a cache eviction timestamp, and a cache miss timestamp.

11. The processor subsystem of claim 9, comprising:

a data structure to store performance events to enable bits that identify items for which events should be profiled.

12. The processor subsystem of claim 9, the performance events comprising cache accesses.

13. The processor subsystem of claim 9, the performance events comprising cache misses.

14. The processor subsystem of claim 10, the performance events tracked at a cache-line granularity.

15. The processor subsystem of claim 10, the performance events tracked at a set of pages granularity.

16. The processor subsystem of claim 9, the tracking component configured to track residency times of cache lines through the one or more caches.

17. The processor subsystem of claim 9, the tracking component configured to provide a thread scheduler with a cache eviction performance event.

18. A computer readable device comprising computer executable instructions that when executed via a processor on a computer system perform a method comprising:

receiving, from an upper layer of software of the computer system, an access behavior description at an intermediary between the upper layer of software and a processor subsystem of the computer system, the access behavior description comprising an indication of how items of a working set are going to be accessed by the upper layer of software when the upper layer of software is executed by the processor subsystem;

determining, by the intermediary, a cache usage management hint based upon a cache configuration of the processor subsystem and the access behavior description specifying a stream access pattern, the cache usage management hint preventing items of the working set from being cached in caches larger than a smallest cache larger than a window corresponding to the stream access pattern; and

providing, by the intermediary, the cache usage management hint to the processor subsystem for consideration by the processor subsystem when performing cache management for at least one cache.

19. The computer readable device of claim 18, the method comprising:

determining the cache usage management hint based upon the access behavior description indicating items of the working set will be accessed by the upper layer of software once, the cache usage management hint specifying the items of the working set are to be stored in memory and not cache.

20. The computer readable device of claim 18, the method comprising:

determining the cache usage management hint based upon the window being larger than a next-to-largest cache, the cache usage management hint specifying a least recently used cache replacement policy.