System including a fine-grained memory and a less-fine-grained memory
First Claim
1. A system comprising:
- a plurality of nodes, each of the nodes comprising a respective processor, a respective interconnect switch, a respective fine-grained memory comprising a plurality of independently-writable words, and a respective less-fine-grained memory comprising a plurality of independently-writable pages, where units of the respective less-fine-grained memory smaller than one of the pages are not independently writable, where each of the pages is at least twice a size of one of the words of the fine-grained memory, and where the respective less-fine-grained memory is a solid-state, non-volatile memory;
an interconnection network coupling the nodes via the respective interconnect switches;
wherein the less-fine-grained memories as an aggregate are configured to store a plurality of elements, each of the elements having a respective element identifier;
wherein the respective fine-grained-memory of each of at least a first subset of the nodes is enabled to store a respective global map, the respective global map configured to specify for each of the elements, based at least in part on a portion of the respective element identifier, a respective home one of the nodes of the element;
wherein, at each of the nodes, the respective less-fine-grained memory is enabled to store a respective subset of the elements, and the respective fine-grained-memory is enabled to store a respective local map, the respective local map having a plurality of entries, each one of the respective subset of the elements associated with a corresponding and distinct one of the entries, each of the entries comprising fields which when populated store a respective physical location of the element associated with the entry, the respective physical location comprising an address of a respective one of the pages of the respective less-fine-grained memory and a respective offset within the respective page;
wherein, at a particular one of the first subset of the nodes, the respective processor is configured to determine, via the respective global map, the respective home node of a particular one of the elements, and forward an access of the particular element to the respective processor of the respective home node of the particular element;
wherein, at the respective home node of the particular element, the respective processor is configured to access, via the respective local map, the respective physical location of the particular element in the respective less-fine-grained memory, and return a response to the access of the particular element to the respective processor of the particular node; and
wherein the particular element and at least one other of the respective subset of the elements of the respective home node of the particular element are enabled to be stored at a same time in the respective page of the respective physical location of the particular element.
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Accused Products
Abstract
A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
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Citations
79 Claims
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1. A system comprising:
- a plurality of nodes, each of the nodes comprising a respective processor, a respective interconnect switch, a respective fine-grained memory comprising a plurality of independently-writable words, and a respective less-fine-grained memory comprising a plurality of independently-writable pages, where units of the respective less-fine-grained memory smaller than one of the pages are not independently writable, where each of the pages is at least twice a size of one of the words of the fine-grained memory, and where the respective less-fine-grained memory is a solid-state, non-volatile memory;
an interconnection network coupling the nodes via the respective interconnect switches;
wherein the less-fine-grained memories as an aggregate are configured to store a plurality of elements, each of the elements having a respective element identifier;
wherein the respective fine-grained-memory of each of at least a first subset of the nodes is enabled to store a respective global map, the respective global map configured to specify for each of the elements, based at least in part on a portion of the respective element identifier, a respective home one of the nodes of the element;
wherein, at each of the nodes, the respective less-fine-grained memory is enabled to store a respective subset of the elements, and the respective fine-grained-memory is enabled to store a respective local map, the respective local map having a plurality of entries, each one of the respective subset of the elements associated with a corresponding and distinct one of the entries, each of the entries comprising fields which when populated store a respective physical location of the element associated with the entry, the respective physical location comprising an address of a respective one of the pages of the respective less-fine-grained memory and a respective offset within the respective page;
wherein, at a particular one of the first subset of the nodes, the respective processor is configured to determine, via the respective global map, the respective home node of a particular one of the elements, and forward an access of the particular element to the respective processor of the respective home node of the particular element;
wherein, at the respective home node of the particular element, the respective processor is configured to access, via the respective local map, the respective physical location of the particular element in the respective less-fine-grained memory, and return a response to the access of the particular element to the respective processor of the particular node; and
wherein the particular element and at least one other of the respective subset of the elements of the respective home node of the particular element are enabled to be stored at a same time in the respective page of the respective physical location of the particular element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
- a plurality of nodes, each of the nodes comprising a respective processor, a respective interconnect switch, a respective fine-grained memory comprising a plurality of independently-writable words, and a respective less-fine-grained memory comprising a plurality of independently-writable pages, where units of the respective less-fine-grained memory smaller than one of the pages are not independently writable, where each of the pages is at least twice a size of one of the words of the fine-grained memory, and where the respective less-fine-grained memory is a solid-state, non-volatile memory;
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43. A method comprising:
- mapping, via a map comprising a plurality of entries, each of a plurality of elements associated via a respective element identifier with a corresponding and distinct one of the entries, the respective element identifier of a particular one of the elements to determine a respective physical location of the particular element in a non-volatile memory, where the non-volatile memory comprises a plurality of pages, where units of the non-volatile memory smaller than one of the pages are not independently writable, and where the respective physical location of the particular element comprises an address of a particular one of the pages and an offset within the particular page;
reading the particular element by retrieving a first portion less than all of the particular page according to the offset, and where at least one of the elements other than the particular element is stored in a second portion of the particular page, the second portion exclusive of the first portion; and
determining if the first portion has an error using a respective portion-specific error-detecting code of the first portion, the respective portion-specific error-detecting code of the first portion stored in the first portion. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79)
- mapping, via a map comprising a plurality of entries, each of a plurality of elements associated via a respective element identifier with a corresponding and distinct one of the entries, the respective element identifier of a particular one of the elements to determine a respective physical location of the particular element in a non-volatile memory, where the non-volatile memory comprises a plurality of pages, where units of the non-volatile memory smaller than one of the pages are not independently writable, and where the respective physical location of the particular element comprises an address of a particular one of the pages and an offset within the particular page;
Specification