Non-volatile memory with guided simulated annealing error correction control

• US 7,975,209 B2
• Filed: 03/31/2007
• Issued: 07/05/2011
• Est. Priority Date: 03/31/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Chin, Henry, Mokhlesi, Nima
• Primary Examiner(s): Lamarre; Guy J
• Application Number:
  US11/694,950
• Publication Number:
  US 20080244367A1
• Time in Patent Office: 1,557 Days
• Field of Search: 714/780, 714/794, 714/795, 375/341, 375/262
• US Class Current: 714/780
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes

Abstract

Data in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data can be performed to. The simulated annealing can introduce randomness, as noise for example, into the decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable.

Claims

1. A non-volatile memory system, comprising:

a set of non-volatile storage elements;

managing circuitry in communication with the set of non-volatile storage elements, the managing circuitry reads information from the set of storage elements by;

reading a set of user data from the set of non-volatile storage elements;

detecting one or more errors associated with the set of user data; and

iteratively decoding the user data using reliability metrics for portions of the set of user data, the decoding includes simulating annealing for one or more portions of user data to cause a change in one or more of the corresponding reliability metrics;

wherein simulating annealing includes guiding the simulated annealing based on a predetermined characterization of the set of non-volatile storage elements; and

wherein the predetermined characterization of the set of non-volatile storage elements includes a predetermined characterization of shifts in threshold voltage of the set of non-volatile storage elements.

2. The non-volatile memory system of claim 1, wherein:

simulating annealing includes introducing a random adjustment to one or more of the reliability metrics.

3. The non-volatile memory system of claim 1, wherein:

simulating annealing includes setting a parameter to influence randomness inserted into the iterative decoding.

4. The non-volatile memory system of claim 3, wherein:

setting the parameter includes setting the parameter based on the one or more errors associated with the set of user data.

5. The non-volatile memory system of claim 4, wherein:

setting the parameter includes setting the parameter to increase the randomness for larger errors associated with the user data.

6. The non-volatile memory system of claim 3, wherein setting the parameter comprises setting the parameter to zero.

7. The non-volatile memory system of claim 1, wherein:

iterative decoding includes, for at least one iteration, determining a predicted value for one or more of the portions of user data to use during a subsequent iteration; and

simulating annealing includes, providing a range of adjustments to the one or more reliability metrics relative to the predicted value and selecting, at least partially at random, one of the adjustments from the range.

8. The non-volatile memory system of claim 7, wherein providing the range of adjustments includes centering the range with respect to the predicted value.

9. The non-volatile memory system of claim 8, wherein providing the range of adjustments includes offsetting the range with respect to the predicted value based on characterizing a data retention property of the set of non-volatile storage elements.

10. The non-volatile memory system of claim 1, wherein:

the iterative decoding is iterative probabilistic decoding;

the reliability metrics are logarithmic likelihood ratios.

11. The non-volatile memory system of claim 10, wherein:

the simulated annealing includes randomly adjusting one or more of the logarithmic likelihood ratios after one or more iterations.

12. The non-volatile memory system of claim 1, wherein:

the set of non-volatile storage elements is a set of NAND flash memory cells.

13. The non-volatile memory system of claim 1, wherein:

the set of non-volatile storage elements is a set of multi-state flash storage elements.

14. The non-volatile memory system of claim 1, wherein:

iteratively decoding the user data includes performing one or more parity checks.

15. The non-volatile memory system of claim 1, wherein:

reading includes at least one of voltage sensing and current sensing.

16. The non-volatile memory system of claim 1, wherein:

the managing circuitry includes at least one of a controller and a state machine.

17. The non-volatile memory system of claim 1, wherein:

the user data includes one or more parity bits.

18. A non-volatile memory system, comprising:

a set of non-volatile storage elements; and

managing circuitry in communication with the set of storage elements, the managing circuitry reads the set of storage elements by;

detecting state information for the set of non-volatile storage elements;

providing one or more code words based on the state information;

detecting one or more errors associated with the one or more code words;

performing a number of iterations of decoding for the one or more code words, wherein decoding includes assigning reliability metrics to bits of the one or more code words and adjusting the reliability metrics for subsequent decoding iterations in an attempt to decrease the one or more errors; and

after the number of iterations, simulating annealing for the one or more code words, wherein simulating annealing includes providing at least a pseudo-random adjustment to one or more of the reliability metrics, the pseudo-random adjustment being based on the one or more errors associated with the one or more code words and a predetermined characterization of shifts in threshold voltage of the set of non-volatile storage elements.

19. A non-volatile memory system, comprising:

a set of non-volatile storage elements;

managing circuitry in communication with the set of non-volatile storage elements, the managing circuitry performs one or more read operations that include;

detecting state information for the set of non-volatile storage elements;

providing one or more code words based on the state information;

detecting one or more errors associated with the one or more code words; and

performing a number of iterations of decoding for the one or more code words, wherein decoding includes assigning reliability metrics to bits of the one or more code words and adjusting the reliability metrics for subsequent decoding iterations in an attempt to decrease the one or more errors,

wherein at least one of the iterations includes guiding an adjustment to at least one reliability metric based on a predetermined characterization of the set of non-volatile storage elements; and

wherein the predetermined characterization of the set of non-volatile storage elements includes a predetermined characterization of shifts in threshold voltage of the set of non-volatile storage elements.