Phase change memory device and method of fabricating the same

• US 7,977,674 B2
• Filed: 09/29/2008
• Issued: 07/12/2011
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Choi, Kyu Jeong, Yoon, Sung Min, Yu, Byoung Gon, Lee, Nam Yeal, Park, Young Sam, Lee, Seung Yun
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Luke; Daniel
• Application Number:
  US12/240,013
• Publication Number:
  US 20090184307A1
• Time in Patent Office: 1,016 Days
• Field of Search: 438102-103, 257/2, 257/42, 257/E31.029
• US Class Current: 257/42
• CPC Class Codes: H10N 70/026 by physical vapor deposition, e.g. sputtering
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A phase change memory device and a method of fabricating the same are provided. A phase change material layer of the phase change memory device is formed of germanium (Ge)-antimony (Sb)-Tellurium (Te)-based Ge₂Sb_2+xTe₅ (0.12≦x≦0.32), so that the crystalline state is determined as a stable single phase, not a mixed phase of a metastable phase and a stable phase, in phase transition between crystalline and amorphous states of a phase change material, and the phase transition according to increasing temperature directly transitions to the single stable phase from the amorphous state. As a result, set operation stability and distribution characteristics of set state resistances of the phase change memory device can be significantly enhanced, and an amorphous resistance can be maintained for a long time at a high temperature, i.e., around crystallization temperature, and thus reset operation stability and rewrite operation stability of the phase change memory device can be significantly enhanced.

Claims

1. A phase change memory device, comprising:

a phase change material layer formed of Ge₂Sb_2+xTe₅ (x>

0) which is a germanium (Ge)-antimony (Sb)-tellurium (Te)-based material, wherein

an excess (x) of antimony is added to Ge₂Sb₂Te₅ to compose the Ge₂Sb_2+xTe₅,

the excess ranges from 0.22 to 0.32, and

the phase change material layer directly transitions from an amorphous phase to a stable hcp crystalline phase without transitioning through a metastable fcc crystalline phase.

2. The phase change memory device according to claim 1, wherein the excess (x) of antimony ranges from 0.22 to 0.27 to maintain an amorphous resistance of the Ge₂Sb_2+xTe₅ at a constant level for a predetermined time under a temperature condition lower than the crystallization temperature of the Ge₂Sb_2+xTe₅ by 30°

C. and to prevent diffusion of the Ge₂Sb_2+xTe₅ into another layer.

3. The phase change memory device according to claim 1, wherein the excess (x) of antimony ranges from 0.22 to 0.27.

4. The phase change memory device according to claim 1, further comprising:

a lower electrode layer formed on a substrate to supply current;

a heat-generating electrode layer formed entirely or partially on a surface of the lower electrode layer to generate heat by the current supplied from the lower electrode layer;

a first insulating layer partially covering the heat-generating electrode layer, having a pore, and partially exposing a surface of the heat-generating electrode layer;

a second insulating layer partially covering the phase change material layer, having a via hole, and partially exposing a surface of the phase change material layer; and

an upper electrode layer formed to fill the via hole.

5. The phase change memory device according to claim 4, wherein the phase change material layer is formed to be in contact with the heat-generating electrode layer exposed through the pore, and fill the pore.

6. The phase change memory device according to claim 4, further comprising:

a diffusion barrier layer interposed between the upper electrode layer and the phase change material layer.

7. The phase change memory device according to claim 1, wherein the phase change memory device is driven by one of a diode, a bipolar transistor and a MOS transistor.

8. The phase change memory device according to claim 7, wherein the MOS transistor has one of a FINFET structure, a structure having a three-dimensional gate electrode, which covers at least sidewalls of a semiconductor active layer to form a channel, and a structure having a plurality of gate electrodes.

9. A method of fabricating a phase change memory device, comprising:

forming a phase change material layer using Ge₂Sb_2+xTe₅ (x>

0) which is a germanium (Ge)-antimony (Sb)-tellurium (Te)-based material, wherein

an excess (x) of antimony is added to Ge₂Sb₂Te₅ to compose the Ge₂Sb_2+xTe₅,

the excess ranges from 0.22 to 0.32 and

the phase change material layer directly transitions from an amorphous phase to a stable hcp crystalline phase without transitioning through a metastable fcc crystalline phase.

10. The method according to claim 9, wherein the composition (x) of antimony added to the Ge₂Sb_2+xTe₅ as an excess ranges from 0.22 to 0.27 to maintain an amorphous resistance of the Ge₂Sb_2+xTe₅ at a constant level for a predetermined time at a temperature lower than the crystallization temperature of the Ge₂Sb_2+xTe₅ by 30°

C. and to prevent diffusion of the Ge₂Sb_2+xTe₅ into another layer.

11. The method according to claim 9, wherein the excess (x) ranges from 0.22 to 0.27.

12. The method according to claim 9, wherein the forming of the phase change material layer comprises respectively adjusting sputtering power applied to a Ge₂Sb₂Te₅ target and an Sb target to control the composition of the Ge₂Sb_2+xTe₅.

13. The method according to claim 9, wherein the forming of the phase change material layer comprises adjusting sputtering power applied to a single target of Ge₂Sb_2+xTe₅ to control the composition of the Ge₂Sb_2+xTe₅.

14. The method according to claim 9, further comprising:

before forming the phase change material layer,

forming a lower electrode layer on a substrate;

entirely or partially forming a heat-generating electrode layer on a surface of the lower electrode layer;

forming a first insulating layer to partially cover the heat-generating electrode layer; and

partially etching the first insulating layer and forming a pore in the first insulating layer to partially expose a surface of the heat-generating electrode layer.

15. The method according to claim 14, wherein after the pore is formed in the first insulating layer, the phase change material layer is formed to be in contact with the heat-generating electrode layer exposed through the pore and fill the pore.

16. The method according to claim 9, further comprising:

after forming the phase change material layer,

forming a second insulating layer on the phase change material layer;

partially etching the second insulating layer and forming a via hole in the second insulating layer to partially expose a surface of the phase change material layer; and

forming an upper electrode layer to be in contact with the phase change material layer exposed through the via hole, and fill the via hole.

17. The method according to claim 16, wherein the second insulating layer is formed by chemical vapor deposition using ECR plasma at room temperature.

18. The method according to claim 16, further comprising:

forming a diffusion barrier layer between the upper electrode layer and the phase change material layer.

19. A phase change memory device, comprising:

a phase change material layer formed of Ge₂Sb_2+xTe₅ (0.27≦

x≦

0.32) which is a germanium (Ge)-antimony (Sb)-tellurium (Te)-based material, wherein

the phase change material layer directly transitions from an amorphous phase to a stable hcp crystalline phase without transitioning through a metastable fcc crystalline phase.