Chip package with die and substrate

• US 7,977,763 B2
• Filed: 11/24/2004
• Issued: 07/12/2011
• Est. Priority Date: 01/19/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): Chambliss; Alonzo
• Application Number:
  US10/996,537
• Publication Number:
  US 20050090099A1
• Time in Patent Office: 2,421 Days
• Field of Search: 438/33, 438/68, 438/108, 438/110, 438/113, 438/114, 438/115, 438/122, 438/458, 438/459, 438/460, 438/462, 438/464, 438/465, 438/622, 438/365, 438/386, 438/387
• US Class Current: 257/516
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Claims

1. A chip package comprising:

a first polymer layer;

a semiconductor die between a first portion of said first polymer layer and a second portion of said first polymer layer, wherein said semiconductor die has a top surface substantially coplanar with a top surface of said first polymer layer;

a second polymer layer on said semiconductor die and said first polymer layers, wherein said second polymer layer has a thickness between 5 and 100 micrometers;

a first patterned metal layer over said semiconductor die, said second polymer layer and said first polymer layer, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said second polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, wherein said first patterned metal layer comprises a piece as a part of a capacitor;

a third polymer layer on said first patterned metal layer and over said second polymer layer, said semiconductor die and said first polymer layer, wherein said third polymer layer has a thickness between 1 and 150 micrometers; and

a metal bump vertically over said first polymer layer, wherein said metal bump is connected to said semiconductor die through said first patterned metal layer.

2. The chip package of claim 1 further comprising a substrate under said semiconductor die and said first and second portions of said first polymer layer.

3. The chip package of claim 2, wherein said substrate comprises glass.

4. The chip package of claim 1, wherein said electroplated metal comprises electroplated copper.

5. The chip package of claim 1, wherein said second polymer layer comprises polyimide.

6. The chip package of claim 1, wherein said first polymer layer comprises an epoxy.

7. The chip package of claim 1 further comprising a second patterned metal layer on said third polymer layer and over said semiconductor die and said first polymer layer, wherein said second patterned metal layer comprises a sputtered metal, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, wherein said metal bump is connected to said first patterned metal layer through said second patterned metal layer.

8. A chip package comprising:

a first polymer layer;

a semiconductor die between a first portion of said first polymer layer and a second portion of said first polymer layer, wherein said semiconductor die has a top surface substantially coplanar with a top surface of said first polymer layer;

a second polymer layer on said semiconductor die and said first polymer layer, wherein said second polymer layer has a thickness between 5 and 100 micrometers;

a first patterned metal layer over said semiconductor die, said second polymer layer and said first polymer layer, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said second polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, wherein said first patterned metal layer comprises a piece as a part of a resistor;

a third polymer layer on said first patterned metal layer and over said second polymer layer, said semiconductor die and said first polymer layer, wherein said third polymer layer has a thickness between 1 and 150 micrometers; and

a metal bump vertically over said first polymer layer, wherein said metal bump is connected to said semiconductor die through said first patterned metal layer.

9. The chip package of claim 8, wherein said electroplated metal comprises electroplated copper.

10. The chip package of claim 8, wherein said first polymer layer comprises an epoxy.

11. The chip package of claim 8, wherein said metal bump comprises a solder.

12. The chip package of claim 8 further comprising a substrate under said semiconductor die and said first and second portions of said first polymer layer.

13. The chip package of claim 12, wherein said substrate comprises glass.

14. The chip package of claim 8 further comprising a second patterned metal layer on said third polymer layer and over said semiconductor die and said first polymer layer, wherein said second patterned metal layer comprises a sputtered metal, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, wherein said metal bump is connected to said first patterned metal layer through said second patterned metal layer.

15. A chip package comprising:

a first polymer layer;

a semiconductor die between a first portion of said first polymer layer and a second portion of said first polymer layer, wherein said semiconductor die has a top surface substantially coplanar with a top surface of said first polymer layer;

a second polymer layer on said semiconductor die and said first polymer layer, wherein said second polymer layer has a thickness between 5 and 100 micrometers;

a first patterned metal layer over said second polymer layer, said semiconductor die and said first polymer layer, wherein said first patterned metal layer is connected to said semiconductor die through an opening in said second polymer layer, wherein said first patterned metal layer comprises an electroplated metal and has a thickness between 1 and 150 micrometers, wherein said first patterned metal layer comprises a piece as a part of an inductor;

a third polymer layer on said first patterned metal layer and over said second polymer layer, said semiconductor die and said first polymer layer, wherein said third polymer layer has a thickness between 1 and 150 micrometers; and

a metal bump vertically over said first polymer layer, wherein said metal bump is connected to said semiconductor die through said first patterned metal layer.

16. The chip package of claim 15, wherein said electroplated metal comprises electroplated copper.

17. The chip package of claim 15, wherein said first polymer layer comprises an epoxy.

18. The chip package of claim 15 further comprising a substrate under said semiconductor die and said first and second portions of said first polymer layer.

19. The chip package of claim 18, wherein said substrate comprises glass.

20. The chip package of claim 15 further comprising a second patterned metal layer on said third polymer layer and over said semiconductor die and said first polymer layer, wherein said second patterned metal layer comprises a sputtered metal, wherein said second patterned metal layer is connected to said first patterned metal layer through an opening in said third polymer layer, wherein said metal bump is connected to said first patterned metal layer through said second patterned metal layer.

21. A chip package comprising:

a first substrate comprising a glass substrate;

a semiconductor die having a bottom surface joined with said first substrate;

a second substrate having a bottom surface joined with a top surface of said semiconductor die, wherein a first opening in said second substrate is vertically over said semiconductor die and passes through said second substrate;

a first metal interconnect in said first opening and over said semiconductor die, wherein said first metal interconnect is connected to said semiconductor die through said first opening, wherein said first metal interconnect comprises electroplated copper; and

a metal bump connected to said semiconductor die through said first metal interconnect and said first opening.

22. The chip package of claim 21, wherein said second substrate comprises a glass substrate.

23. The chip package of claim 21, wherein said first metal interconnect is further over a top surface of said second substrate.

24. The chip package of claim 21 further comprising a dielectric layer on said first metal interconnect, wherein a second opening in said dielectric layer is over a contact point of said first metal interconnect, and said contact point is at a bottom of said second opening, wherein said metal bump is connected to said contact point through said second opening.

25. The chip package of claim 24 further comprising a second metal interconnect on a top surface of said dielectric layer and on said contact point, wherein said second metal interconnect comprises an electroplated metal, wherein said second metal interconnect is connected to said first metal interconnect through said second opening, wherein said metal bump is connected to said first metal interconnect through said second metal interconnect.

26. The chip package of claim 21, wherein said first metal interconnect extends across an edge of said semiconductor die.

27. The chip package of claim 21, wherein said top surface of said semiconductor die is an active surface of said semiconductor die.

28. The chip package of claim 21, wherein said bottom surface of said semiconductor die is at a backside of said semiconductor die.

29. The chip package of claim 21, wherein said metal bump is horizontally offset from said first opening.