Fusion quad flat semiconductor package

• US 7,977,774 B2
• Filed: 07/10/2007
• Issued: 07/12/2011
• Est. Priority Date: 07/10/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, GiJeong, Choi, YeonHo, Kim, WanJong
• Primary Examiner(s): Gurley; Lynne A
• Assistant Examiner(s): Gebreyesus; Yosef
• Application Number:
  US11/775,566
• Publication Number:
  US 20090014851A1
• Time in Patent Office: 1,463 Days
• Field of Search: 257/666, 257/669, 257/676, 257/670, 257/672, 257/E33.06, 257/E23.031, 257/E23.042, 257/E23.045, 257/E23.048, 257/E23.049, 257/E23.052, 257/E23.066, 257/E23.141, 257/784, 257/787, 438/124, 438/111, 438/123, 438/25, 438/26
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor package comprising:

a generally planar die paddle defining multiple peripheral edge segments;

a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first and second leads; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads and the semiconductor die such that the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die paddle and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the second leads protrude from respective ones of the side surfaces of the package body.

2. The semiconductor package of claim 1 wherein the die paddle has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

3. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the first and second leads by conductive wires which are covered by the package body.

4. The semiconductor package of claim 3 wherein:

each of the first leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die paddle and defining a terminal which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the second leads includes a wire bond zone and an outer end portion, the downset of each of the second leads extending between the wire bond zone and the outer end portion thereof; and

the conductive wires extend from the semiconductor die to respective ones of the wire bond zones of the first leads and second leads.

5. The semiconductor package of claim 4 wherein the conductive wires further extend to the outer end portions of certain ones of the second leads which do not include a downset formed therein.

6. The semiconductor package of claim 4 wherein:

the die paddle and the inner end portions of the first leads extend along a first plane;

the wire bond zones of the first and second leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the outer end portions of the first and second leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

7. The semiconductor package of claim 4 wherein portions of the outer end portions of the second leads protrude from respective ones of the side surfaces of the package body and are bent to assume a gull-wing configuration.

8. A semiconductor package comprising:

a generally planar die paddle defining multiple peripheral edge segments;

a plurality of first leads segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a plurality of third leads, at least some of which include a downset formed therein, the third leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first, second and third leads; and

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the first and second leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the third leads protrude from respective ones of the side surfaces of the package body.

9. The semiconductor package of claim 8 wherein at least some of the first leads are integrally connected to the die paddle and define signal pins.

10. The semiconductor package of claim 8 wherein at least some of the first leads are formed to include an enlarged locking tip structure to facilitate the anchoring thereof to the package body.

11. The semiconductor package of claim 8 wherein the die paddle has a generally quadrangular configuration, and the first, second and third leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die paddle.

12. The semiconductor package of claim 8 wherein the semiconductor die is electrically connected to the first, second and third leads by conductive wires which are covered by the package body.

13. The semiconductor package of claim 12 wherein:

each of the first leads defines a terminal which is exposed in the bottom surface of the package body;

each of the second leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die paddle and defining a terminal which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the third leads includes a wire bond zone and an outer end portion, the downset of each of the third leads extending between the wire bond zone and the outer end portion thereof; and

the conductive wires extend from the semiconductor die to respective ones of the first leads and the wire bond zones of the second leads and third leads.

14. The semiconductor package of claim 13 wherein the conductive wires further extend to the outer end portions of certain ones of the third leads which do not include a downset formed therein.

15. The semiconductor package of claim 13 wherein:

the die paddle, the first leads and the inner end portions of the second leads extend along a first plane;

the wire bond zones of the second and third leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the outer end portions of the second and third leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

16. The semiconductor package of claim 13 wherein portions of the outer end portions of the third leads protrude from respective ones of the side surfaces of the package body and are bent to assume a gull-wing configuration.

17. The semiconductor package of claim 13 wherein the terminal defined by each of the first leads is linearly aligned with the terminal defined by a respective one of the second leads.

18. The semiconductor package of claim 13 wherein the outer end portions of the second leads and at least some of the third leads each include an angled section.

19. A semiconductor package comprising:

a die paddle;

a plurality of first leads extending along the die paddle;

a plurality of second leads which each include first and second downsets formed therein in spaced relation to each other, the second leads extending along the die paddle;

a plurality of third leads, at least some of which include a downset formed therein, the third leads extend along the die paddle;

a semiconductor die attached to the die paddle and electrically connected to at least one of each of the first, second and third leads; and

a package body defining a bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die paddle and the first and second leads are exposed in the bottom surface of the package body, and portions of the third leads protrude from respective ones of the side surfaces of the package body.

20. The semiconductor package of claim 19 wherein:

each of the first leads defines a terminal which is exposed in the bottom surface of the package body;

each of the second leads includes an inner end portion, a wire bond zone, and an outer end portion, the inner end portion being disposed between the first downset thereof and the die paddle and defining a terminal which is exposed in the bottom surface of the package body, the first downset extending between the inner end portion and the wire bond zone thereof, and the second downset extending between the wire bond zone and the outer end portion thereof;

each of the third leads includes a wire bond zone and an outer end portion, the downset of each of the third leads extending between the wire bond zone and the outer end portion thereof; and

conductive wires extend from the semiconductor die to respective ones of the first leads and the wire bond zones of the second leads and third leads.