Integrated circuit with contact region and multiple etch stop insulation layer

• US 7,977,797 B2
• Filed: 08/11/2009
• Issued: 07/12/2011
• Est. Priority Date: 09/02/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Li, Wenmei, Hui, Angela T., Hopper, Dawn, Ghandehari, Kouros
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US12/539,480
• Publication Number:
  US 20090294969A1
• Time in Patent Office: 700 Days
• Field of Search: 438/639
• US Class Current: 257/760
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

Claims

1. An integrated circuit comprising

a substrate for providing an electrical well for said integrated circuit;

a contact region coupled to said substrate, said contact region provides an electrical path to and from said substrate;

a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and

a multiple etch stop insulation layer coupled to said contact region, wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region, and wherein said multiple etch stop insulation layer includes;

a first etch stop layer directly on said substrate in said contact region;

a first sub interlevel dielectric layer over said first etch stop layer;

a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and

a second sub interlevel dielectric layer over said second etch stop layer.

2. An integrated circuit of claim 1 wherein said first etch stop layer protects removal of a substrate material by an etch process.

3. An integrated circuit of claim 1 wherein said first sub interlevel dielectric layer insulates said contact region.

4. An integrated circuit of claim 1 wherein said second etch stop layer protects lower layers during an etching process.

5. An integrated circuit of claim 1 wherein said second sub interlevel dielectric layer insulates said contact region.

6. An integrated circuit of claim 1 wherein said spacer region insulates said contact region.

7. An integrated circuit of claim 1 wherein said substrate coupling area of said contact region permits multiple active regions to be arranged relatively close to one another while a metal layer coupling area of said contact region is larger than said substrate coupling area of said contact region to provide better process window with desired critical dimension (CD).

8. An integrated circuit of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Å

thick, said first sub interlevel dielectric layer is in a range of about 1,000 to 2,000 Å

thick, said second etch stop layer is in a range of about 300 to 800 Å

thick and said second sub interlevel dielectric layer is in a range of about 10K Å

±

1K Å

thick.

9. An integrated circuit of claim 1 wherein an area of a first space in a portion of said first sub interlevel dielectric layer for said contact region is in a first range of about 0.06 μ

m to 0.13 μ

m wide and an area of a second space in said second sub interlevel dielectric layer for said contact region is in a second range of about 0.16 μ

m to 0.18 μ

m wide.

10. An integrated circuit of claim 1 further comprising depositing an anti reflective coating layer.

11. An integrated circuit comprising:

a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics, said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer, wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer, wherein said multiple etch stop insulation layer is formed utilizing a lithography process;

a contact region in said multiple etch stop insulation layer, wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer, wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom, such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region.

12. An integrated circuit of claim 11 wherein said first etch stop layer is in a range of about 300 to 800 Å

thick, said first sub interlevel dielectric layer is in a range of about 1,000 to 2,000 Å

thick, said second etch stop layer is in a range of about 300 to 800 Å

thick and said second sub interlevel dielectric layer is in a range of about 10K Å

±

1K Å

thick.

13. An integrated circuit of claim 11 further comprising a floating gate.

14. An integrated circuit of claim 11 further comprising depositing an anti reflective coating layer.

15. An integrated circuit of claim 11 wherein a bottom of said contact region is a first range of about 0.06 μ

m to 0.13 μ

m wide and a top of said contact region is in a second range of about 0.16 μ

m to 0.18 μ

m wide.