Integrated circuit with contact region and multiple etch stop insulation layer
DCFirst Claim
1. An integrated circuit comprisinga substrate for providing an electrical well for said integrated circuit;
- a contact region coupled to said substrate, said contact region provides an electrical path to and from said substrate;
a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and
a multiple etch stop insulation layer coupled to said contact region, wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region, and wherein said multiple etch stop insulation layer includes;
a first etch stop layer directly on said substrate in said contact region;
a first sub interlevel dielectric layer over said first etch stop layer;
a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and
a second sub interlevel dielectric layer over said second etch stop layer.
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Accused Products
Abstract
The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
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Citations
15 Claims
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1. An integrated circuit comprising
a substrate for providing an electrical well for said integrated circuit; -
a contact region coupled to said substrate, said contact region provides an electrical path to and from said substrate; a spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and a multiple etch stop insulation layer coupled to said contact region, wherein said multiple etch stop insulation layer provides electrical insulation between other regions of said integrated circuit and isolates guidance of electrical current flow in said contact region, and wherein said multiple etch stop insulation layer includes; a first etch stop layer directly on said substrate in said contact region; a first sub interlevel dielectric layer over said first etch stop layer; a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and a second sub interlevel dielectric layer over said second etch stop layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit comprising:
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a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics, said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer, wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer, wherein said multiple etch stop insulation layer is formed utilizing a lithography process; a contact region in said multiple etch stop insulation layer, wherein creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer, wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom, such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region. - View Dependent Claims (12, 13, 14, 15)
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Specification