Boost and up-down switching regulator with synchronous freewheeling MOSFET

• US 7,977,926 B2
• Filed: 04/21/2008
• Issued: 07/12/2011
• Est. Priority Date: 07/06/2007
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): Behm; Harry
• Assistant Examiner(s): Grubb; Matthew
• Application Number:
  US12/148,576
• Publication Number:
  US 20090010035A1
• Time in Patent Office: 1,177 Days
• Field of Search: 323/222, 323/223, 323/225, 323/230, 323/268, 323/282, 363/127
• US Class Current: 323/223
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

A freewheeling MOSFET is connected in parallel with the inductor in a switched DC/DC converter. When the freewheeling MOSFET is turned on during the switching operation of the converter, while the low-side and energy transfer MOSFETs are turned off, the inductor current circulates or “freewheels” through the freewheeling MOSFET. The frequency of the converter is thereby made independent of the lengths of the magnetizing and energy transfer stages, allowing far greater flexibility in operating and converter and overcoming numerous problems associated with conventional DC/DC converters. For example, the converter may operate in either step-up or step-down mode and may even transition for one mode to the other as the values of the input voltage and desired output voltage vary.

Claims

1. A DC/DC voltage converter comprising:

an inductor and a low-side switch connected in a series conduction path between first and second supply voltages, the inductor being coupled to the first supply voltage and the low-side switch being coupled to the second supply voltage, a V_x node being located in the series conduction path between the inductor and the low-side switch;

an energy transfer switch connected between the V_x node and an output terminal of the converter; and

a freewheeling switch connected in parallel with the inductor, the freewheeling switch comprising a freewheeling MOSFET and a body bias generator, the body bias generator being coupled to each of first and second conduction terminals and a body of the freewheeling MOSFET, the body bias generator being adapted to short the body to one of the first and second conduction terminals of the freewheeling MOSFET responsive to a relationship between voltages present at the first and second conduction terminals, respectively, of the freewheeling MOSFET so as to prevent any P-N junction in the freewheeling MOSFET from becoming forward-biased.

2. The DC/DC voltage converter of claim 1 wherein the body bias generator comprises a first body bias MOSFET coupled between the body and the first conduction terminal of the freewheeling MOSFET and a second body bias MOSFET coupled between the body and the second conduction terminal of the freewheeling MOSFET, a gate of the first body bias MOSFET being coupled to the second conduction terminal of the freewheeling MOSFET, and a gate of the second body bias MOSFET being coupled to the first conduction terminal of the freewheeling MOSFET.

3. The DC/DC voltage converter of claim 2 comprising a voltage clamping circuit connected in parallel with the freewheeling MOSFET, the voltage clamping circuit comprising a clamping diode connected in series with a parallel combination of a blocking diode and a clamping switch, the blocking diode and the clamping diode being oriented so as to oppose a flow of current in either direction through the voltage clamping circuit when the clamping switch is open, the clamping switch being responsive to an output signal from a comparator, respective input terminals of the comparator being connected such that the comparator compares a value of the first supply voltage and a value of an output voltage at the output terminal.

4. The DC/DC voltage converter of claim 3 wherein the clamping switch and the blocking diode are integral to a clamping MOSFET, a gate buffer being connected between an output terminal of the comparator and a gate terminal of the clamping MOSFET.

5. The DC/DC voltage converter of claim 4 wherein the comparator and the gate buffer are arranged so as to cause the clamping MOSFET to be ON when the first supply voltage is greater than the output voltage and OFF when the first supply voltage is less than the output voltage.

6. The DC/DC voltage converter of claim 1 wherein the energy transfer switch comprises a synchronous rectifier MOSFET and a second body bias generator, the second body bias generator being coupled to each of first and second conduction terminals and a body of the synchronous rectifier MOSFET, the second body bias generator being adapted to short the body to one of the first and second conduction terminals of the synchronous rectifier MOSFET responsive to a relationship between voltages present at the first and second conduction terminals, respectively, of the synchronous rectifier MOSFET so as to prevent any P-N junction in the synchronous rectifier MOSFET from becoming forward-biased.

7. The DC/DC voltage converter of claim 6 wherein the second body bias generator comprises a third body bias MOSFET coupled between the body and the first conduction terminal of the synchronous rectifier MOSFET and a fourth body bias MOSFET coupled between the body and the second conduction terminal of the synchronous rectifier MOSFET, a gate of the third body bias MOSFET being coupled to the second conduction terminal of the synchronous rectifier MOSFET, and a gate of the fourth body bias MOSFET being coupled to the first conduction terminal of the synchronous rectifier MOSFET.

8. The DC/DC voltage converter of claim 7 comprising a voltage clamping circuit connected in parallel with the synchronous rectifier MOSFET, the voltage clamping circuit comprising a clamping diode connected in series with a parallel combination of a blocking diode and a clamping switch, the blocking diode and the clamping diode being oriented so as to oppose a flow of current in either direction through the voltage clamping circuit when the clamping switch is open, the clamping switch being responsive to an output signal from a comparator, respective input terminals of the comparator being connected such that the comparator compares a value of the first supply voltage and a value of an output voltage at the output terminal.

9. The DC/DC voltage converter of claim 8 wherein the clamping switch and the blocking diode are integral to a clamping MOSFET, a gate buffer being connected between an output terminal of the comparator and a gate terminal of the clamping MOSFET.

10. The DC/DC voltage converter of claim 9 wherein the comparator and the gate buffer are arranged so as to cause the clamping MOSFET to be OFF when the first supply voltage is greater than the output voltage and ON when the first supply voltage is less than the output voltage.

11. The DC/DC voltage converter of claim 1 wherein the energy transfer switch comprises a diode.

12. The DC/DC voltage converter of claim 1 wherein the freewheeling MOSFET comprises a P-channel MOSFET, a gate of the P-channel MOSFET being driven by a gate buffer coupled to the first supply voltage.

13. The DC/DC voltage converter of claim 1 wherein the freewheeling MOSFET comprises a N-channel MOSFET, a gate of the N-channel MOSFET being driven by a gate buffer, the gate buffer being coupled to a bootstrap circuit, the bootstrap circuit comprising a bootstrap diode and a bootstrap capacitor connected in series between the first supply voltage and the Vx node, a voltage supply terminal of the gate buffer being coupled to a node between the bootstrap diode and the bootstrap capacitor.

14. A DC/DC voltage converter comprising:

an inductor and a low-side switch connected in a series conduction path between first and second supply voltages, the inductor being coupled to the first supply voltage and the low-side switch being coupled to the second supply voltage, a V_x node being located in the series conduction path between the inductor and the low-side switch;

an energy transfer switch connected between the V_x node and an output terminal of the converter; and

a freewheeling switch connected in parallel with the inductor, the freewheeling switch comprising a freewheeling MOSFET and a body bias generator with integrated adaptive clamping, the body bias generator comprising a first body bias MOSFET coupled between a body and a first conduction terminal of the freewheeling MOSFET and a second body bias MOSFET coupled between the body and a second conduction terminal of the freewheeling MOSFET, a gate of the first body bias MOSFET being coupled to the second conduction terminal of the freewheeling MOSFET, a gate of the second body bias MOSFET being coupled to a gate buffer and the gate buffer being coupled to a comparator, respective input terminals of the comparator being connected such that the comparator compares a value of the first supply voltage and a value of an output voltage at the output terminal.

15. The DC/DC voltage converter of claim 14 wherein the comparator and the gate buffer are arranged so as to cause the second body bias MOSFET to be ON when the first supply voltage is greater than the output voltage and OFF when the first supply voltage is less than the output voltage.

16. The DC/DC voltage converter of claim 15 wherein the energy transfer switch comprises a synchronous rectifier MOSFET and a second body bias generator with integrated adaptive clamping, the second body bias generator comprising a third body bias MOSFET coupled between a body and a first conduction terminal of the synchronous rectifier MOSFET and a fourth body bias MOSFET coupled between the body and a second conduction terminal of the synchronous rectifier MOSFET, a gate of the third body bias MOSFET being coupled to the second conduction terminal of the synchronous rectifier MOSFET, a gate of the fourth body bias MOSFET being coupled to a second gate buffer and the second gate buffer being coupled to a second comparator, respective input terminals of the second comparator being connected such that the second comparator compares a value of the first supply voltage and a value of the an output voltage at the output terminal.

17. The DC/DC voltage converter of claim 16 wherein the second comparator and the second gate buffer are arranged so as to cause the fourth body bias MOSFET to be OFF when the first supply voltage is greater than the output voltage and ON when the first supply voltage is less than the output voltage.

18. The DC/DC voltage converter of claim 17 wherein the comparator and the second comparator are comprised within a single comparator.

19. A DC/DC voltage converter comprising:

an inductor and a low-side switch connected in a series conduction path between first and second supply voltages, the inductor being coupled to the first supply voltage and the low-side switch being coupled to the second supply voltage, a V_x node being located in the series conduction path between the inductor and the low-side switch;

an energy transfer switch connected between the V_x node and an output terminal of the converter;

a freewheeling switch connected in parallel with the inductor; and

an adaptive clamping circuit comprising a clamping diode connected to the V_x node, the adaptive clamping circuit being adapted to clamp the Vx node to either the first supply voltage or an output voltage at the output terminal depending on a relationship between the first supply voltage and the output voltage.

20. The DC/DC voltage converter of claim 19 wherein the adaptive clamping circuit clamps the Vx node to the first supply voltage when the converter is operating in a step-down mode and to the output voltage when the converter is operating in a step-up mode.

21. The DC/DC voltage converter of claim 20 wherein the adaptive clamping circuit further comprises an analog multiplexer and a comparator, an anode terminal of the diode being coupled to the Vx node, a cathode terminal of the diode being coupled to an output terminal of the analog multiplexer, an output terminal of the comparator being coupled to a signal input terminal of the analog multiplexer, a first input terminal of the comparator and a first voltage supply terminal of the analog multiplexer being coupled to the first supply voltage, and a second input terminal of the comparator and a second voltage supply terminal of the analog multiplexer being coupled to the output voltage.

22. A method of converting a DC input voltage to a DC output voltage comprising:

applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to magnetize the inductor;

disconnecting the second terminal of the inductor from the circuit ground;

coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal;

disconnecting the second terminal of the inductor from the capacitor and the output terminal;

connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal;

with the first and second terminals of the inductor connected together, detecting the value of a decreasing current through the inductor; and

disconnecting the first and second terminals of the inductor when the detected value of the current through the inductor falls below a predetermined level.

23. The method of claim 22 comprising:

providing a first break-before-make interval between disconnecting the second terminal of the inductor from circuit ground and coupling the second terminal of the inductor to the capacitor and the output terminal; and

during the first break-before-make interval, coupling the anode of a clamping diode to the second terminal of the inductor and connecting the cathode of the clamping diode to the higher of the DC input voltage and the DC output voltage, thereby limiting a rise in a voltage at the second terminal of the inductor during the first break-before-make interval.

24. The method of claim 23 comprising:

providing a second break-before-make interval between disconnecting the second terminal of the inductor from the capacitor and the output terminal and connecting the first and second terminals of the inductor together; and

during the second break-before-make interval, coupling the anode of the clamping diode to the second terminal of the inductor and connecting the cathode of the clamping diode to the higher of the DC input voltage and the DC output voltage, thereby limiting a rise in a voltage at the second terminal of the inductor during the second break-before-make interval.

25. The method of claim 22 wherein the DC output voltage is higher than the DC input voltage.

26. The method of claim 22 wherein the DC output voltage is lower than the DC input voltage.

27. The method of claim 22 wherein connecting the first and second terminals of the inductor together comprises:

connecting a freewheeling MOSFET between the first and second terminals of the inductor; and

turning the freewheeling MOSFET on.

28. The method of claim 27 comprising controlling the voltage of a body of the freewheeling MOSFET so as to prevent any P-N junction in the freewheeling MOSFET from becoming forward-biased.

29. The method of claim 22 wherein coupling the second terminal of the inductor to the capacitor and the output terminal comprises:

connecting an energy transfer MOSFET between the second terminal of the inductor and the capacitor and the output terminal; and

turning the energy transfer MOSFET on.

30. The method of claim 29 comprising controlling the voltage of a body of the energy transfer MOSFET so as to prevent any P-N junction in the energy transfer MOSFET from becoming forward-biased.

31. A DC/DC voltage converter comprising:

an inductor and a low-side switch connected in a series conduction path between first and second supply voltages, the inductor being coupled to the first supply voltage and the low-side switch being coupled to the second supply voltage, a V_x node being located in the series conduction path between the inductor and the low-side switch;

an energy transfer switch connected between the V_x node and an output terminal of the converter, the energy transfer switch comprising a synchronous rectifier MOSFET and a body bias generator, the body bias generator being coupled to each of first and second conduction terminals and a body of the synchronous rectifier MOSFET, the body bias generator being adapted to short the body to one of the first and second conduction terminals of the synchronous rectifier MOSFET responsive to a relationship between voltages present at the first and second conduction terminals, respectively, of the synchronous rectifier MOSFET so as to prevent any P-N junction in the synchronous rectifier MOSFET from becoming forward-biased; and

an adaptive clamping circuit comprising a clamping diode connected to the V_x node, the adaptive clamping circuit being adapted to clamp the Vx node to either the first supply voltage or an output voltage at the output terminal depending on a relationship between the first supply voltage and the output voltage.

32. The DC/DC voltage converter of claim 31 wherein the adaptive clamping circuit clamps the Vx node to the first supply voltage when the converter is operating in a step-down mode and to the output voltage when the converter is operating in a step-up mode.

33. The DC/DC voltage converter of claim 32 wherein the adaptive clamping circuit further comprises an analog multiplexer and a comparator, an anode terminal of the diode being coupled to the Vx node, a cathode terminal of the diode being coupled to an output terminal of the analog multiplexer, an output terminal of the comparator being coupled to a signal input terminal of the analog multiplexer, a first input terminal of the comparator and a first voltage supply terminal of the analog multiplexer being coupled to the first supply voltage, and a second input terminal of the comparator and a second voltage supply terminal of the analog multiplexer being coupled to the output voltage.

34. A method of converting a DC input voltage to a DC output voltage comprising:

(a) during a time interval t_ON, applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to magnetize the inductor;

(b) at the termination of the time interval t_ON, disconnecting the second terminal of the inductor from the circuit ground;

(c) during a time interval t_XFER, coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal;

(d) at the termination of the time interval t_XFER, disconnecting the second terminal of the inductor from the capacitor and the output terminal;

(e) during a time interval t_FW, connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal; and

(f) at the termination of the time interval t_FW, disconnecting the first and second terminals of the inductor;

repeating (a)-(f) in the same sequence multiple times, wherein at each repetition t_ON +t_XFER +t_FW equals a time period T; and

while repeating (a)-(f) in the same sequence multiple times, varying the length of at least one of the time intervals t_oN and t_XFER while adjusting the time interval t_FW as required to maintain the time period T at a first fixed value and to maintain the DC output voltage at a second fixed value;

the method comprising performing (b) immediately after (a), (e) immediately after (b), (f) immediately after (e), (c) immediately after (f) and (d) immediately after (c).

35. A method of converting a DC input voltage to a DC output voltage comprising:

(a) during a time interval t_ON, applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to magnetize the inductor;

(b) at the termination of the time interval t_ON, disconnecting the second terminal of the inductor from the circuit ground;

(c) during a time interval t_XFER, coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal;

(d) at the termination of the time interval t_XFER, disconnecting the second terminal of the inductor from the capacitor and the output terminal;

(e) during a time interval t_FW, connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal; and

(f) at the termination of the time interval t_FW, disconnecting the first and second terminals of the inductor; and

repeating (a)-(f) in the same sequence multiple times, while maintaining t_oN at a first fixed value and adjusting the length of at least one of the time intervals t_xFER and t_FW as required to maintain the DC output voltage at a second fixed value;

the method comprising performing (b) immediately after (a), (e) immediately after (b), (f) immediately after (e), (c) immediately after (f) and (d) immediately after (c).

36. A method of converting a DC input voltage to a DC output voltage comprising:

(a) during a time interval t_ON, applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to magnetize the inductor;

(b) at the termination of the time interval t_ON, disconnecting the second terminal of the inductor from the circuit ground;

(c) during a time interval t_XFER, coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal;

(d) at the termination of the time interval t_XFER, disconnecting the second terminal of the inductor from the capacitor and the output terminal;

(e) during a time interval t_FW, connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal; and

(f) at the termination of the time interval t_FW, disconnecting the first and second terminals of the inductor; and

repeating (a)-(f) in the same sequence multiple times, while maintaining t_FW at a fixed value.

37. The method of claim 36 comprising performing (b) immediately after (a), (c) immediately after (b), (d) immediately after (c), (e) immediately after (d) and (f) immediately after (e).

38. The method of claim 36 comprising performing (b) immediately after (a), (e) immediately after (b), (f) immediately after (e), (c) immediately after (f) and (d) immediately after (c).

39. A method of converting a DC input voltage to a DC output voltage comprising:

(a) during a time interval t_ON, applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to magnetize the inductor;

(b) at the termination of the time interval t_ON, disconnecting the second terminal of the inductor from the circuit ground;

(c) during a time interval t_XFER, coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal;

(d) at the termination of the time interval t_XFER, disconnecting the second terminal of the inductor from the capacitor and the output terminal;

repeating (a)-(d) multiple times while detecting the DC output voltage; and

when the detected DC output voltage is greater than a target level, performing the following (e) and (f) at least once;

(e) during a time interval t_FW, connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal; and

(f) at the termination of the time interval t_FW, disconnecting the first and second terminals of the inductor from each other.

40. The method of claim 39 wherein the duration of the time interval t_FW is adjusted such that t_ON +t_XFER +t_FW equals a fixed clock cycle T.

41. The method of claim 39 further comprising:

detecting a value of a current though the inductor during the time interval t_FW; and

disconnecting the first and second terminals of the inductor from each other when the detected value of the current through the inductor falls below a predetermined value.

42. The method of claim 39 further comprising:

detecting a value of the output voltage during the time interval t_FW; and

disconnecting the first and second terminals of the inductor from each other when the detected value of the output voltage falls below a target value.

43. A method of converting a DC input voltage to a DC output voltage comprising:

(a) during a time interval t_ON, applying the DC input voltage to a first terminal of an inductor while coupling a second terminal of the inductor to a circuit ground so as to provide an inductor current through the inductor;

(b) at the termination of the time interval t_ON, disconnecting the second terminal of the inductor from the circuit ground;

(c) during a time interval t_XFER, coupling the second terminal of the inductor to a capacitor and an output terminal so as to provide the DC output voltage at the output terminal and to provide a load current to a load connected to the output terminal;

(d) at the termination of the time interval t_XFER, disconnecting the second terminal of the inductor from the capacitor and the output terminal;

(e) during a time interval t_FW, connecting the first and second terminals of the inductor together while the second terminal of the inductor is disconnected from the capacitor and the output terminal; and

(f) at the termination of the time interval t_FW, disconnecting the first and second terminals of the inductor from each other;

repeating (a)-(f) in the same sequence multiple times,

wherein a level of the inductor current remains above a level of the load current during all of said time intervals.