Method and apparatus for testing devices using serially controlled intelligent switches
First Claim
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1. A probe card assembly, comprising:
- a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line;
wherein each of the switches can open or close a circuit through the switch; and
wherein each of the switches is configured to open if a current level through the circuit exceeds a threshold value,wherein each of the switches is configured to open responsive to a programmable current level, andeach of the switches is configured to open responsive to the programmable current level existing for a programmable debounce period.
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Abstract
Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.
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Citations
11 Claims
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1. A probe card assembly, comprising:
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a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line; wherein each of the switches can open or close a circuit through the switch; and wherein each of the switches is configured to open if a current level through the circuit exceeds a threshold value, wherein each of the switches is configured to open responsive to a programmable current level, and each of the switches is configured to open responsive to the programmable current level existing for a programmable debounce period. - View Dependent Claims (2, 3, 4)
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5. A probe card assembly, comprising:
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a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line, wherein each of the switches comprises; a switch circuit having a first terminal, a second terminal, and a control terminal; a current sensor coupled to each of the first terminal and the second terminal, the current sensor having an output terminal; and debounce logic coupled between the control terminal of the switch circuit and the output terminal of the current sensor.
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6. A test assembly, comprising:
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a printed wiring board including connectors for connecting to test instruments, and a serial control line providing a control signal; a probe head supporting test probes; and at least one integrated circuit (IC) coupled to the serial control line, the at least one IC including switches coupled to at least a portion of the test probes, each of the switches being programmable responsive to the control signal transmitted as a sequential bit stream on the serial control line, where each of the switches is configured to open responsive to a programmable current level existing for a programmable debounce period.
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7. A method of testing components on a wafer using a probe card assembly, comprising:
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serially shifting a control signal through a chain comprising a plurality of integrated circuits (ICs) including a plurality of switches, the plurality of switches being programmed responsive to the control signal; communicating test signals between test probes and test instruments through the plurality of switches to test the components; and wherein the act of serially shifting comprises loading first bits of the control signal into a shift register of each of the plurality of ICs, the first bits selectively enabling a programmable current trip and a current sensing capability for each of the plurality of switches. - View Dependent Claims (8, 9, 10, 11)
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Specification