Apparatus and methods for through substrate via test

• US 7,977,962 B2
• Filed: 07/15/2008
• Issued: 07/12/2011
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hargan, Ebrahim H, King, Gregory, Dimitriu, Dragos, Bunker, Layne
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): BENITEZ ROSARIO, JOSHUA
• Application Number:
  US12/173,722
• Publication Number:
  US 20100013512A1
• Time in Patent Office: 1,092 Days
• Field of Search: 324/158.1, 324/765, 257/774
• US Class Current: 324/762.01
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/816 for an application-specific layout
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/014 Solder alloys

Abstract

A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.

Claims

1. An apparatus, comprising:

a floating potential reference, the floating potential reference being a first voltage reference source;

a plurality of operational amplifiers in a first chip of a plurality of chips, the plurality of chips arranged in a vertical stack, each one connected between the floating potential reference and a top portion of one of a plurality of series connected electrical through substrate vias in the vertical stack;

a plurality of enable switches in a second chip of the plurality of chips in the vertical stack, each connected between a bottom portion of the plurality of series connected electrical through substrate vias and a second potential reference, the second potential reference being a second voltage reference source;

a first resistor connected between the second potential reference and a power supply; and

a second resistor connected between the second potential reference and a bottom portion of a test series connected electrical through substrate vias, where a top portion of the test series connected electrical through substrate vias are connected to the floating potential reference.

2. The apparatus of claim 1, wherein the test series connected electrical through substrate vias are formed as a reference to be substantially identical to each one of the plurality of series connected electrical through substrate vias to be measured.

3. The apparatus of claim 1, comprising:

a current source connected to the top portion of one of the plurality of series connected electrical through substrate vias and one of the plurality of operational amplifiers.

4. An apparatus, comprising:

a first voltage reference source;

a plurality of operational amplifiers connected to the first voltage reference source in a first chip of a plurality of chips, the plurality of chips arranged in a vertical stack, each of the plurality of operational amplifiers connected to an end of one of a plurality of series connected electrical through substrate vias in the vertical stack; and

a second end of each of the plurality of series connected electrical through substrate vias connected to a second voltage reference source in a second chip of the plurality of chips.

5. The apparatus of claim 4, wherein the first voltage reference source comprises a variable first voltage reference source.

6. The apparatus of claim 5, further comprising a control circuit connected to the variable first voltage reference source to set a selected series of voltage levels to the operational amplifiers during a test procedure.

7. The apparatus of claim 4, further comprising a plurality of current sources connected to one of the plurality of operational amplifiers and the plurality of series connected electrical through substrate vias.

8. The apparatus of claim 4, further comprising a plurality of enable transistors connected between the second end of the plurality of series connected electrical through substrate vias and the second voltage reference source.

9. An apparatus, comprising:

a first potential reference, the first potential reference being a first voltage reference source;

at least two operational amplifiers in a first chip of a plurality of chips, the plurality of chips arranged in a vertical stack, each operational amplifier connected to the first potential reference, a current source, and a first end of a plurality of series connected electrical through substrate vias in the vertical stack;

at least one state machine connected to the first potential reference and a first end of a series connected group of test through substrate vias, each of the series connected group of test through substrate vias also connected to an enable transistor connected to a portion of circuitry having a selected resistance and capacitance; and

a second potential reference connected to a second end of the plurality of series connected electrical through substrate vias in a second chip of the plurality of chips in the vertical stack, the second potential reference connected to a termination resistor connected to a second end of the series connected group of test through substrate vias, the second potential reference being a second voltage reference source.

10. The apparatus of claim 9, further comprising a first potential reference source enabled to vary during at least one of apparatus testing or apparatus operation.

11. The apparatus of claim 10, further comprising a control circuit connected to vary the first voltage reference source in accordance with at least one of a preselected pattern or in response to test conditions.

12. The apparatus of claim 9, wherein the at least one state machine comprises at least one of a micro processor, a ring oscillator, or a variable delay line.