Signal delay circuit

• US 7,977,993 B2
• Filed: 05/20/2008
• Issued: 07/12/2011
• Est. Priority Date: 12/31/2007
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lu, Hung-Wen, Su, Chau-Chin
• Primary Examiner(s): Luu; An T
• Application Number:
  US12/123,613
• Publication Number:
  US 20090167399A1
• Time in Patent Office: 1,148 Days
• Field of Search: 327/261, 327/263, 327/264, 327/407, 327/408, 327/410, 326/23, 326/24, 326 26- 28, 326/93, 326 95- 96, 326/104, 326/106, 326/408
• US Class Current: 327/264
• CPC Class Codes: H03H 11/26 Time-delay networks analogue shift registers G11C27/04
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00228 having complementary input and output signals
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A signal delay circuit including a capacitive load element is described. The capacitive load element has a first input end, a second input end, and a third input end. The first input end receives a first signal, the second input end receives a second signal inverted to the first signal, and the third input end receives a control signal. The capacitance of the capacitive load element changes with the control signal.

Claims

1. A signal delay circuit for receiving a first signal and outputting a second signal, the signal delay circuit, comprising:

a conventional inverter for directly, without any intervening elements, receiving and inverting the first signal, so as to output a completely inverted signal as the second signal; and

a capacitive load element, having a first input end directly, without any intervening elements, receiving the first signal, a second input end directly, without any intervening elements, receiving the second signal, and a third input end receiving a control signal, wherein the capacitance of the capacitive load element changes with the control signal;

wherein the transmission delay between the first signal and the second signal is increased with the increase of the capacitance of the capacitive load element.

2. The signal delay circuit as claimed in claim 1, wherein the capacitive load element at least comprises three switches.

3. The signal delay circuit as claimed in claim 1, wherein the capacitive load element is an NAND gate.

4. The signal delay circuit as claimed in claim 3, wherein in a steady state, an N-type transistor in the NAND gate is turned off.

5. The signal delay circuit as claimed in claim 3, wherein when the first signal is approximately equal to the second signal, the N-type transistor in the NAND gate is slightly turned on.

6. The signal delay circuit as claimed in claim 1, wherein the capacitive load element is an NOR gate.

7. The signal delay circuit as claimed in claim 6, wherein in a steady state, an P-type transistor in the NOR gate is turned off.

8. The signal delay circuit as claimed in claim 6, wherein when the first signal is approximately equal to the second signal, the P-type transistor in the NOR gate is slightly turned on.

9. The signal delay circuit as claimed in claim 1, wherein the capacitive load element has a floating output.

10. A signal delay circuit, for receiving a first input signal and a second input signal and outputting a first signal and a second signal, the signal delay circuit, comprising:

a first conventional inverter, for directly, without any intervening elements, receiving the first input signal so as to output the first signal after completely inverting the first input signal; and

a second conventional inverter, for directly, without any intervening elements, receiving the second input signal so as to output the second signal after completely inverting the second input signal, wherein the second signal is an inverted signal of the first signal, and the first input signal and the second input signal are differential input signals; and

more than one capacitive load element, each having a first input end directly, without any intervening elements, receiving the first signal, a second input end directly, without any intervening elements, receiving the second signal, and a third input end receiving a control signal, wherein the capacitance of the capacitive load element changes with the control signal.

11. The signal delay circuit as claimed in claim 10, wherein the capacitive load element at least comprises three switches.

12. The signal delay circuit as claimed in claim 10, wherein the capacitive load element is an NAND gate.

13. The signal delay circuit as claimed in claim 12, wherein in a steady state, an N-type transistor in the NAND gate is turned off.

14. The signal delay circuit as claimed in claim 12, wherein when the first signal is approximately equal to the second signal, the N-type transistor in the NAND gate is slightly turned on.

15. The signal delay circuit as claimed in claim 10, wherein the capacitive load element is an NOR gate.

16. The signal delay circuit as claimed in claim 15, wherein in a steady state, an P-type transistor in the NOR gate is turned off.

17. The signal delay circuit as claimed in claim 15, wherein when the first signal is approximately equal to the second signal, the P-type transistor in the NOR gate is slightly turned on.

18. The signal delay circuit as claimed in claim 10, wherein the first input signal and the second input signal are differential input signals.

19. The signal delay circuit as claimed in claim 10, wherein the capacitive load element has a floating output.