Signal processing circuit, low-voltage signal generator and image display incorporating the same

• US 7,978,169 B2
• Filed: 02/21/2008
• Issued: 07/12/2011
• Est. Priority Date: 05/18/2001
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Kubota, Yasushi, Washio, Hajime, Cairns, Graham Andrew, Yamashita, Hidehiko, Brownlow, Michael James
• Primary Examiner(s): Xiao; Ke
• Application Number:
  US12/071,529
• Publication Number:
  US 20080150924A1
• Time in Patent Office: 1,237 Days
• Field of Search: 345 98-104, 326 62- 79
• US Class Current: 345/100
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

There are provided: a first logic operation circuit which performs a logic operation using a high-amplitude logic signal; a transmission system having a load capacitance; and a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal for output to the transmission system. In the configuration, the first logic operation circuit operates based on a high-amplitude logic signal, and is therefore free from malfunctions and performs operations at high speed. Further, the transmission system introducing a load capacitance transmits a low-amplitude logic signal and therefore restrains increases in electric power consumption and occurrence of unnecessary radiation.

Claims

1. A signal processing circuit comprising:

a first step-up level shifter which transforms an incoming low-amplitude clock signal from a control circuit to a high-amplitude clock signal having a higher amplitude than the incoming low-amplitude clock signal;

a first logic operation circuit operating at a first voltage which performs a logic operation using the high-amplitude logic output signal of the first step-up level shifter;

a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal;

a second step-up level shifter which transforms the incoming low-amplitude signal from the low-voltage signal generator to a high-amplitude signal having a higher amplitude than the incoming low-amplitude signal, and

a second logic operation circuit operating at the first voltage which performs a logic operation using the high-amplitude signal of the second step-up level shifter.

2. The signal processing circuit as set forth in claim 1, wherein at least the first logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.

3. The signal processing circuit as set forth in claim 1, wherein at least the second logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.

4. A low-voltage signal generator provided in a signal processing circuit, said signal processing circuit including:

a first step-up level shifter which transforms an incoming low-amplitude clock signal from a control circuit to a high-amplitude clock signal having a higher amplitude than the incoming low-amplitude clock signal;

a first logic operation circuit operating at a first voltage which performs a logic operation using the high-amplitude logic output signal of the first step-up level shifter;

wherein the low-voltage signal generator transforms the high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal;

a second step-up level shifter which transforms the incoming low-amplitude signal from the low-voltage signal generator to a high-amplitude signal having a higher amplitude than the incoming low-amplitude signal, and

a second logic operation circuit operating at the first voltage which performs a logic operation using the high-amplitude signal of the second step-up level shifter.

5. The low-voltage signal generator as set forth in claim 4, comprising transistors forming a gate circuit, wherein:

each transistor belongs to either a low level output group or a high level output group;

each transistor belonging to the low level output group is fed at a gate thereof with the high-amplitude logic signal and at an input end thereof with any one of a low-amplitude logic signal which remains at a low level throughout a period in which the high-amplitude logic signal is applied to the gate, a low level potential from a low level source for use to produce the low-amplitude logic signal, and a low level potential from a high level source for use to produce the high-amplitude logic signal, and outputs a low level potential of a low-amplitude logic signal through an output end thereof; and

each transistor belonging to the high level output group is fed at a gate thereof with the high-amplitude logic signal and at an input end thereof with either one of a low-amplitude logic signal which remains at a high level throughout the period and a high level potential from the low level source, and outputs a high level potential of a low-amplitude logic signal through an output end thereof.

6. The low-voltage signal generator as set forth in claim 5, wherein:

the signal processing circuit is used in an image display including pixels arranged in a matrix, data signal lines each provided for a different column of pixels, scan signal lines each provided for a different row of pixels, a data signal line drive circuit driving the data signal lines, and a scan signal line drive circuit driving the scan signal lines;

the low-amplitude logic signal which remains at a low level throughout the period is a start pulse signal representing when the data signal line drive circuit starts to operate; and

the low-amplitude logic signal which remains at a high level throughout the period is an inverse signal of the start pulse signal.

7. The low-voltage signal generator as set forth in the claim 5, wherein each transistor outputs the low-amplitude logic signal and an inverse signal thereof.

8. The low-voltage signal generator as set forth in the claim 4, constituted by a silicon thin film transistor made of polysilicon.

9. An image display, comprising:

pixels arranged in a matrix;

data signal lines each provided for a different column of pixels;

scan signal lines each provided for a different row of pixels;

a data signal line drive circuit driving the data signal lines; and

a scan signal line drive circuit driving the scan signal lines, wherein

either one, or both, of the data signal line drive circuit and the scan signal line drive circuit include(s);

a first step-up level shifter which transforms an incoming low-amplitude clock signal from a control circuit to a high-amplitude clock signal having a higher amplitude than the incoming low-amplitude clock signal;

a first logic operation circuit operating at a first voltage which performs a logic operation using the high-amplitude logic output signal of the first step-up level shifter;

a low-voltage signal generator which is a step-down level shifter transforming an incoming high-amplitude logic signal from the first logic operation circuit to a low-amplitude logic signal having a lower amplitude than the high-amplitude logic signal;

a second step-up level shifter which transforms the incoming low-amplitude signal from the low-voltage signal generator to a high-amplitude signal having a higher amplitude than the incoming low-amplitude signal, and

a second logic operation circuit operating at the second voltage which performs a logic operation using the high-amplitude signal of the second step-up level shifter.

10. The image display as set forth in claim 9, wherein

the first logic operation circuit is a clock frequency dividing circuit for dividing a clock signal in terms of frequency,

the second logic operation circuit comprises shift registers connected in series, and

the shift registers are connected to the second step-up level shifters respectively.

11. The image display as set forth in claim 9, wherein

the first logic operation circuit is an inverse clock signal circuit which produces an inverse clock signal from a clock signal,

the second logic operation circuit comprises shift registers connected in series, and

the shift registers are connected to the second step-up level shifters respectively.

12. The image display as set forth in claim 9, wherein

the data signal line drive circuit includes the step-down level shifter which is the low-voltage signal generator,

the first logic operation circuit is a circuit in which shift registers are connected in series and is a first shift register circuit which is a circuit determining a timing to sample digital data, and

the second logic operation circuit is a circuit in which shift registers are connected in series and is a second shift register circuit which is a circuit determining a timing to output to the data signal lines.

13. The image display as set forth in claim 9, wherein at least the first logic operation circuit is constituted by a silicon thin film transistor made of polysilicon.