Raster-order pixel dithering
First Claim
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1. An apparatus for generating stochastic dither values in raster order for pixels of a frame, comprising:
- a raster address generator that is configured to generate line and column addresses in a raster order;
a first register and a second register, wherein;
the first register is configured to store a current value X0 of the second register in response to a new line signal and to store a value of (M+A) mod C in response to a new column signal, where M is a current value of the first register, A is a constant, and C is a number of pixels in a line; and
the second register is configured to store a value of (X0+B) mod C in response to the new line signal, where B is a constant, and where A, B and C are mutually prime; and
an output configured to provide the value in the first register as a dither value.
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Abstract
Stochastic dithering may be used to reduce the size of the frame buffer and the complexity of the D/A Converters (DACs) in the drive circuitry that are used in a video display system. Hardware for stochastic dithering can be simplified when pixel data is presented in raster order. The hardware adds algebraic noise to the image to be dithered, and thresholds the result.
6 Citations
20 Claims
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1. An apparatus for generating stochastic dither values in raster order for pixels of a frame, comprising:
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a raster address generator that is configured to generate line and column addresses in a raster order; a first register and a second register, wherein; the first register is configured to store a current value X0 of the second register in response to a new line signal and to store a value of (M+A) mod C in response to a new column signal, where M is a current value of the first register, A is a constant, and C is a number of pixels in a line; and the second register is configured to store a value of (X0+B) mod C in response to the new line signal, where B is a constant, and where A, B and C are mutually prime; and an output configured to provide the value in the first register as a dither value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for generating stochastic dither values in raster order for pixels of a frame, comprising:
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generating line and column addresses in a raster order; storing, in a first register, a current value X0 of a second register in response to a new line signal and a value of (M+A) mod C in response to a new column signal, where M is a current value of the first register, A is a constant, and C is a number of pixels in a line; storing, in the second register, a value of (X0+B) mod C in response to the new line signal, where B is a constant, and where A, B and C are mutually prime; and outputting the value in the first register as a dither value. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus for dithering reduced-bit depth pixels, comprising:
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means for generating line and column addresses in a raster order; first and second means for storing, wherein; the first means for storing is configured to store a current value X0 of the second means for storing in response to a new line signal and to store a value of (M+A) mod C in response to a new column signal, where M is a current value of the first means for storing, A is a constant, and C is a number of pixels in a line; and the second means for storing is configured to store a value of (X0+B) mod C in response to the new line signal, where B is a constant, and where A, B and C are mutually prime; and means for outputting the value in the first register as a dither value. - View Dependent Claims (18)
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19. An apparatus for dithering raster-order image data, comprising:
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a dither matrix generation circuit; and an adder circuit configured to add first, second, and third dither matrix values from the dither matrix generation circuit to first, second, and third color components, respectively, of the image data; wherein the dither matrix generation circuit comprises a first register and a second register; wherein the first register is configured to store a current value X0 of the second register in response to a new line signal and to store a value of (M+A) mod C in response to a new column signal, where M is a current value of the first register, A is a constant, and C is a constant; wherein the second register is configured to store a value of (X0+B) mod C in response to the new line signal, where B is a constant, and where A, B, and C are mutually prime; and wherein the first dither matrix value is the value in the first register, the second dither matrix value is a value of a first function of the first dither matrix value, and the third dither matrix value is a value of a second function of the first dither matrix value. - View Dependent Claims (20)
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Specification