Circuit arrangement comprising an electronic component and an ESD protection arrangement

• US 7,978,451 B2
• Filed: 09/12/2008
• Issued: 07/12/2011
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mayerhofer, Michael, Hell, Magnus-Maria, Mergens, Markus
• Primary Examiner(s): Nguyen; Danny
• Application Number:
  US12/209,307
• Publication Number:
  US 20090073620A1
• Time in Patent Office: 1,033 Days
• Field of Search: 361/56, 361/111
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

A description is given of a circuit arrangement including at least one electronic component having first and second terminals, and comprising an ESD protection arrangement against disturbance pulses, is the ESD protection arrangement connected via connection terminals in parallel with the electronic component between the first and second terminals. The ESD protection arrangement includes a first ESD protection unit and a second ESD protection unit, that is connected in parallel with the first ESD protection unit and that reacts more rapidly than the first protection unit to a voltage rise at the connection terminals with the formation of a conductive current path between the connection terminals.

Claims

1. A circuit arrangement comprising:

an electronic component having first and second terminals; and

an ESD protection arrangement against disturbance pulses, which is coupled via connection terminals in parallel with the electronic component between the first and second terminals, the ESD protection arrangement comprising;

a first ESD protection unit; and

a second ESD protection unit, coupled in parallel with the first ESD protection unit, wherein the second ESD protection unit reacts more rapidly than the first ESD protection unit to a voltage rise at the connection terminals with a formation of a conductive current path between the connection terminals, wherein

the second ESD protection unit comprises a MOS transistor having load path terminals coupled between the first and second terminals and having a control terminal, the control terminal of the MOS transistor being short-circuited with one of the load path terminals or being coupled to one of the load path terminals via a resistor, and

the MOS transistor of the second ESD protection unit comprises a cellularly constructed MOS transistor having a first number of transistor cells.

2. The circuit arrangement as claimed in claim 1, wherein the first ESD protection unit has a higher current-carrying capacity than the second ESD protection unit.

3. The circuit arrangement as claimed in claim 1, wherein the first ESD protection unit comprises a zener diode or a MOS transistor.

4. The circuit arrangement as claimed in claim 3, wherein the first ESD protection unit comprises a MOS transistor having a load path coupled between the first and second terminals and having a control terminal, the control terminal of the MOS, transistor being short-circuited with one of the load path terminals or being coupled to one of the load path terminals via a resistor.

5. The circuit arrangement as claimed in claim 1, further comprising a voltage limiting element coupled in parallel with the resistor.

6. The circuit arrangement as claimed in claim 5, wherein the voltage limiting element comprises a zener diode.

7. The circuit arrangement as claimed in claim 1, wherein the electronic component comprises a cellularly constructed MOS transistor having a second number of transistor cells.

8. The circuit arrangement as claimed in claim 1, wherein the electronic component and the first ESD protection unit are integrated in a common semiconductor body.

9. The circuit arrangement as claimed in claim 1, wherein the first number of transistor cells is between about 10³ and about 10⁵, and wherein the second number of transistor cells is between about 200 and about 500.

10. The circuit arrangement as claimed in claim 5, wherein the resistor has a resistance between about 100Ω

and about 1000Ω

.

11. The circuit arrangement as claimed in claim 1 wherein the electronic component comprises an active semiconductor component.

12. The circuit arrangement as claimed in claim 1, wherein the electronic component comprises a passive component.

13. The circuit arrangement as claimed in claim 12, wherein the passive component comprises a capacitance integrated in or on a semiconductor body.

14. The circuit arrangement as claimed in claim 1, wherein the electronic component comprises a microelectromechanical system.

15. A method of operating a circuit arrangement comprising an electronic component having first and second terminals, the method comprising:

receiving a disturbance voltage between the first and second terminals;

switching on a first ESD protection unit coupled via first and second terminals in parallel with the electronic component between the first and second terminals, switching on the first ESD unit comprising forming a conductive current path between the first and second terminals, wherein

the first ESD protection unit comprises a MOS transistor having load path terminals coupled between the first and second terminals and having a control terminal, the control terminal of the MOS transistor being short-circuited with one of the load path terminals or being coupled to one of the load path terminals via a resistor, and

the MOS transistor of the first ESD protection unit comprises a cellularly constructed MOS transistor having a second number of transistor cells; and

after switching on the first ESD protection unit, switching on a second ESD protection unit coupled between the first and second terminals.

16. The method of claim 15, wherein the first ESD protection unit reacts faster than the second ESD protection unit.

17. The method of claim 15, wherein switching on the first ESD protection unit comprises switching on the first ESD protection unit when the disturbance voltage reaches a first voltage level.

18. The method of claim 17, wherein switching on the second ESD protection unit comprises clamping the first and second terminals to a second voltage level, the second voltage level less than the first voltage level.

19. The method of claim 17, wherein the electronic component comprises a cellularly constructed MOS transistor having a second number of transistor cells.

20. A circuit arrangement comprising:

an electronic component having first and second terminals, the electronic component comprising a cellularly constructed MOS transistor having a first number of transistor cells; and

an ESD protection arrangement against disturbance pulses, which is coupled via connection terminals in parallel with the electronic component between the first and second terminals, the ESD protection arrangement comprising;

a first ESD protection unit; and

a second ESD protection unit, coupled in parallel with the first ESD protection unit, wherein the second ESD protection unit reacts more rapidly than the first ESD protection unit to a voltage rise at the connection terminals with a formation of a conductive current path between the connection terminals, wherein

the second ESD protection unit comprises a MOS transistor having load path terminals coupled between the first and second terminals and having a control terminal, the control terminal of the MOS transistor being short-circuited with one of the load path terminals or being coupled to one of the load path terminals via a resistor, and

the MOS transistor of the second ESD protection unit comprises a cellularly constructed MOS transistor having a second number of transistor cells.