Flash memory controller having reduced pinout

• US 7,978,516 B2
• Filed: 04/08/2008
• Issued: 07/12/2011
• Est. Priority Date: 12/27/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Pliant Technology, Inc. (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): Reidlinger; R Lance
• Application Number:
  US12/082,205
• Publication Number:
  US 20090168525A1
• Time in Patent Office: 1,190 Days
• Field of Search: 365/185.05, 365/185.11, 365/191, 711/5, 711/103
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.

Claims

1. A storage system comprising:

an integrated circuit device comprising a memory controller, the integrated circuit device including a plurality of pins;

first and second integrated circuit flash memory devices;

the first flash memory device having a first chip select pin and a first ready-busy pin, the second flash memory device having a second chip select pin and a second ready-busy pin;

a first signal path connecting the first chip select pin and the first ready-busy pin to a first memory controller pin; and

a second signal path connecting the second chip select pin and the second ready-busy pin to a second memory controller pin;

whereby the first memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the first flash memory device and the second memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the second flash memory device.

2. The system as in claim 1, further including:

third and fourth integrated circuit flash memory devices;

the third flash memory device having a third chip select pin and a third ready-busy pin, the fourth flash memory device having a fourth chip select pin and a fourth ready-busy pin;

a third signal path connecting the third chip select pin and the third ready-busy pin to the first memory controller pin; and

a fourth signal path connecting the fourth chip select pin and the fourth ready-busy pin to the second memory controller pin;

whereby the first memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the first and third flash memory devices and the second memory controller pin serves as a communication path for both ready-busy and chip select signals transmitted to and/or received from the second and fourth flash memory devices.

3. The system as in claim 2, further including:

first circuitry that acts as a logical and gate connecting the first and third ready-busy pins; and

second circuitry that acts as a logical and gate connecting the second and fourth ready-busy pins;

whereby a ready signal is received on the first memory controller pin only if both the first and third ready-busy pins are in the ready state and a ready signal is received on the second memory controller pin only if both the second and fourth ready-busy pins are in the ready state.

4. The system as in claim 3, further including:

logic that controls each chip select and ready-busy signal path so that either the chip select or the ready-busy signal can be active at a given time on a particular path, but not both.

5. The system as in claim 4, in which:

the logic causes the same chip select signal to be transmitted simultaneously from the first memory controller pin to the first and third chip select pins, thereby causing the first and third flash memory devices to be simultaneously selected.

6. A storage system comprising:

a storage controller;

a first and a second flash memory bank, each made up of a plurality of connected flash memory devices, each flash memory device including a chip select pin and a ready-busy pin;

a first signal path connecting the chip select and ready-busy pins of the flash memory devices in the first flash memory bank with a first storage controller pin;

a second signal path connecting the chip select and ready-busy pins of the flash memory devices in the second flash memory bank with a second storage controller pin;

whereby each signal path is operable in at least two modes, in a first of which the signal path conveys ready-busy information from the ready-busy pins of the flash memory bank to the corresponding controller pin and in a second of which the signal path conveys chip select information from the controller pin to the chip select pins of the corresponding flash memory bank.

7. The system as in claim 6 in which:

the first signal path conveys a ready signal from the ready-busy pins of the flash memory devices in the first flash memory bank to the first storage controller pin only if all of the ready-busy pins of the first flash memory bank devices indicate a ready state, and

the second signal path conveys a ready signal from the ready-busy pins of the flash memory devices in the second flash memory bank to the second storage controller pin only if all of the ready-busy pins of the second flash memory bank devices indicate a ready state.

8. The system as in claim 7, in which:

the first signal path simultaneously conveys a chip select signal from the first storage controller pin to the chip select pin of each flash memory device in the first flash memory bank; and

the second signal path simultaneously conveys a chip select signal from the second storage controller pin to the chip select pin of each flash memory device in the second flash memory bank.

9. The system as in claim 8, in which:

the first and second signal paths each include an inverter that inverts the signal output from the corresponding storage controller pin prior to receipt of the signal at the flash memory device chip select pins.

10. The system as in claim 9, in which:

the first and second signal paths each include a connection between the flash memory device ready-busy pins and ground.

11. A storage system comprising:

a group of flash memory integrated circuit devices, each flash memory integrated circuit device including;

a first flash die and a second flash die;

one ready/busy pin per die, each such pin attached to one of the two dice, but not the other;

one chip select pin per die, each such pin attached to one of the two dice, but not the other; and

a plurality of address, command and/or data pins, each attached to both dice;

a storage controller disposed on one or more integrated circuit devices, the storage controller integrated circuit device(s) including a plurality of pins, the pins including;

a first storage controller pin directly or indirectly connected to the ready/busy and chip select pins associated with the first flash die of each flash memory integrated circuit device, but not connected to the ready/busy pins and chip select pins associated with the second flash die of each flash memory integrated circuit device;

a second storage controller pin directly or indirectly connected to the ready/busy pins and chip select pins associated with the second flash die of each flash memory integrated circuit device, but not connected to the ready/busy pins and chip select pins associated with the first flash die of each flash memory integrated circuit device; and

a plurality of pins directly or indirectly connected to the plurality of flash memory address, command and/or data pins.

12. The storage system of claim 11, further including:

a first signal path between the first storage controller pin and the first flash die ready/busy and chip select pins, the signal path carrying a ready signal from the ready/busy pins of the first flash die of each flash memory integrated circuit device to the first storage controller pin, and carrying a chip select signal from the first storage controller pin to the chip select pins of the first flash die of each flash memory integrated circuit device; and

a second signal path between the second storage controller pin and the second flash die ready/busy and chip select pins, the signal path carrying a ready signal from the ready/busy pins of the second flash die of each flash memory integrated circuit device to the second storage controller pin, and carrying a chip select signal from the second storage controller pin to the chip select pins of the second flash die of each flash memory integrated circuit device;

whereby the same chip select signal is delivered from the first storage controller pin to the chip select pins of the first flash die of each flash memory integrated circuit device, the same chip select signal is delivered from the second storage controller pin to the chip select pins of the first flash die of each flash memory integrated circuit device, a ready signal is delivered to the first storage controller pin if the ready/busy pins of the first flash die of each flash memory integrated circuit device is indicating a ready state and a ready signal is delivered to the second storage controller pin if the ready/busy pins of the second flash die of each flash memory integrated circuit device is indicating a ready state.

13. The storage system of claim 12, in which:

the first and second signal paths each include an inverter between the first and second storage controller pins and the flash die chip select pins so that the signal delivered to the flash die chip select pins is inverted from the signal output on the storage controller pins.

14. The storage system of claim 13, in which:

the first and second signal paths each include a pullup directly or indirectly attached to the ready/busy pins.

15. The storage system of claim 14, in which:

the first storage controller pin is directly or indirectly connected to at least four first flash die ready/busy and chip select pins; and

the second storage controller pin is directly or indirectly connected to at least four second flash die ready/busy and chip select pins.

16. A method of operating a system including a storage controller connected to a group of flash memory devices comprising first and second memory banks, each bank consisting of a plurality of such devices, each of the flash memory devices including a ready/busy pin and a chip select pin, the method comprising the following steps:

(a) receiving a first ready signal on a first storage controller pin, the first ready signal generated as a result of a ready signal transmitted by the ready/busy pins of each of the flash memory devices in the first memory bank;

(b) at least in part in response to receipt of the first ready signal, generating a first chip select signal and transmitting it through the first storage controller pin for receipt by chip select pins of each of the first memory bank flash memory devices.

17. The method as in claim 16, further including:

inverting the first chip select signal prior to receipt of the signal at the chip select pins.

18. The method as in claim 16, further including:

(c) receiving a second ready signal on a second storage controller pin, the second ready signal generated as a result of a ready signal transmitted by the ready/busy pins of each of the flash memory devices in the second memory bank;

(d) at least in part in response to receipt of the second ready signal, generating a second chip select signal and transmitting it through the second storage controller pin for receipt by chip select pins of each of the second memory bank flash memory devices.

19. The method as in claim 18, in which steps (c) and (d) overlap steps (a) and (b) in time, whereby the first and second storage controller pins transmit an active chip select signal to the first and second banks at the same time.

20. The method as in claim 19, further including:

(e) transmitting first address information on pins of the storage controller;

(f) the first memory bank devices latching the first address information, the latching occurring at least in part in response to the receipt of the first chip select signal from the first storage controller pin;

(g) transmitting second address information on pins of the storage controller;

(h) the second memory bank devices latching the second address information, the latching occurring at least in part in response to the receipt of the second chip select signal from the second storage controller pin, the second address information being different from the first address information.

21. A system including a storage controller and a storage module comprising a plurality of flash memory devices organized into a first and a second memory bank, in which:

the storage controller includes a first group of pins directly or indirectly connected to the first memory bank and a second group of pins directly or indirectly connected to the second memory bank;

the first group of pins including

a first pin that in a first mode receives a ready/busy signal generated by anding together signals from a separate ready/busy pin associated with each flash device of the first memory bank, and in a second mode transmits a chip select signal to separate chip select pins associated with each flash device of the first memory bank, the chip select signal being transmitted simultaneously to each of the first memory bank chip select pins;

and a first set of pins operable in a first mode to simultaneously transmit the same command to pins of each flash device of the first memory bank, in a second mode to simultaneously transmit the same address to pins of each flash device of the first memory bank and in a third mode to simultaneously transmit data to pins of each flash device of the first memory bank, the data transmitted to each flash device being different;

the second group of pins including

a second pin that in a first mode receives a ready/busy signal generated by anding together signals from a separate ready-busy pin associated with each flash device of the second memory bank, and in a second mode transmits a chip select signal to separate chip select pins associated with each flash device of the second memory bank, the chip select signal being transmitted simultaneously to each of the second memory bank chip select pins;

and a second set of pins operable in a first mode to simultaneously transmit the same command to pins of each flash device of the second memory bank, in a second mode to simultaneously transmit the same address to pins of each flash device of the second memory bank and in a third mode to simultaneously transmit data to pins of each flash device of the second memory bank, the data transmitted to each flash device being different;

whereby the first and second group of pins operate independently, such that transmission of any of the described signals on the first group of pins may overlap transmission of any of the described signals on the second group of pins.

22. The system of claim 21, in which the storage module further comprises a third memory bank and in which:

the first group of pins includes a third pin, that in a first mode receives a ready/busy signal generated by anding together signals from a separate ready-busy pin associated with each flash device of the third memory bank, and in a second mode transmits a chip select signal to separate chip select pins associated with each flash device of the third memory bank, the chip select signal being transmitted simultaneously to each of the third memory bank chip select pins;

whereby the first pin and the third pin are not operable simultaneously.

23. The system of claim 22, in which:

the first set of pins is operable in a fourth mode to simultaneously transmit the same command to pins of each flash device of the third memory bank, in a fifth mode to simultaneously transmit the same address to pins of each flash device of the third memory bank and in a sixth mode to simultaneously transmit data to pins of each flash device of the third memory bank, the data transmitted to each flash device being different.

24. The system of claim 23, further including:

a first inverter disposed between the first pin and the chip select pins of the flash devices of the first memory bank, and

a second inverter disposed between the second pin and the chip select pins of the flash devices of the second memory bank.

25. The system of claim 24, further including:

a first pullup operatively connectable to the ready/busy pins of the flash devices of the first memory bank, and

a second pullup operatively connectable to the ready/busy pins of the flash devices of the second memory bank.