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NAND flash memory

  • US 7,978,517 B2
  • Filed: 03/08/2010
  • Issued: 07/12/2011
  • Est. Priority Date: 08/16/2006
  • Status: Expired due to Fees
First Claim
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1. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising:

  • a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof,whereina first bit line that is selected is charged when the p-type semiconductor substrate is set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are in a floating state.

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