NAND flash memory
First Claim
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1. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising:
- a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof,whereina first bit line that is selected is charged when the p-type semiconductor substrate is set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are in a floating state.
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Abstract
A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of the memory cell units having a plurality of electrically rewritable memory cells that are connected to each other, wherein a bit line that is selected by a sense amplifier is charged in a state where a drain-side select gate line, a source-side select gate line and a p-type semiconductor substrate are set at a ground potential, and source lines, n-type wells, p-type wells, and a bit line that is not selected by the sense amplifier are in a floating state.
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Citations
12 Claims
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1. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising:
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a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof, wherein a first bit line that is selected is charged when the p-type semiconductor substrate is set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are in a floating state. - View Dependent Claims (2, 3, 4)
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5. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising:
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a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof, wherein a first bit line that is selected is charged to a first potential at the same time as the p-type semiconductor substrate being set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected being charged to a second potential that is between said first potential and said ground potential. - View Dependent Claims (6, 7, 8)
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9. A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, comprising:
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a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a hit line and is connected to a drain-side select gate line at a first gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at a second gate thereof, wherein a first bit line that is selected is charged to a first potential while the p-type semiconductor substrate is being set at a ground potential, and the source lines, the n-type wells, the p-type wells, and a second bit line that is not selected are being charged to a second potential that is between said first potential and said ground potential. - View Dependent Claims (10, 11, 12)
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsIsobe, Katsuaki
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Primary Examiner(s)PHAN, TRONG Q
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Application NumberUS12/719,686Publication NumberTime in Patent Office491 DaysField of Search365/185.11, 365/185.17, 365/185.18, 365/185.23, 365/185.25, 365/185.26, 365/185.27, 365/185.33, 365/185.29US Class Current365/185.11CPC Class CodesG11C 16/0483 comprising cells having sev...G11C 8/08 Word line control circuits,...G11C 8/10 Decoders
