Semiconductor device having resistance based memory array, method of reading, and systems associated therewith

• US 7,978,539 B2
• Filed: 11/28/2008
• Issued: 07/12/2011
• Est. Priority Date: 03/21/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Byung Gil, Lee, Kwang Jin
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US12/292,891
• Publication Number:
  US 20090237978A1
• Time in Patent Office: 956 Days
• Field of Search: 365/189.15, 365/148, 365/189.07, 365/189.05
• US Class Current: 365/189.15
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 15/00 Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
• CPC Class Codes: G11C 15/046 using non-volatile storage elements
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

Claims

1. A semiconductor device, comprising:

a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell;

a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and

a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

2. The semiconductor device of claim 1, wherein the write address buffer is configured to compare the read address to valid write addresses stored in the write address buffer.

3. The semiconductor device of claim 2, wherein the write address buffer is configured to maintain a flag associated with each write address stored in the write address buffer, and the flag indicates whether the associated write address is valid.

4. The semiconductor device of claim 3, further comprising:

a validity timer configured to measure a validity time period, the validity timer being reset in response to a received write command; and

wherein

the write address buffer is configured to set the validity flags to an invalid state in response to expiration of the validity time period.

5. The semiconductor device of claim 1, wherein the read unit is configured to apply a lower read current if no match between the read address and one of the stored write addresses exits than if a match between the read address and one of the stored write addresses exits and the indication indicates that the settling time has not expired.

6. The semiconductor device of claim 1, wherein the read unit is configured to apply a lower read current if the indication indicates that the settling time has expired than if a match between the read address and one of the stored write addresses exits and the indication indicates that the settling time has not expired.

7. The semiconductor device of claim 1, wherein the read unit includes a timer measuring a time period equal to or greater than an amount of time for data written in the non-volatile memory cell array to settle.

8. The semiconductor device of claim 1, wherein the read unit comprises:

a read circuit configured to apply the read current to the non-volatile memory cell array;

a voltage generator configured to supply operational voltages; and

a selector configured to select at least one of the operational voltages for use by the read circuit in applying the read current, the selector selecting the operational voltage based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.

9. The semiconductor device of claim 8, wherein

the read circuit is configured to apply one of a first current based on a first operational voltage and a second current based on a second operational voltage, the second current being less than the first current;

and

the selector is configured to select the first operational voltage if the read address matches one of the stored write addresses and the indication indicates that the settling time has not expired.

10. The semiconductor device of claim 9, wherein

the selector is configured to select the second operational voltage if the read address does not match one of the stored write address.

11. The semiconductor device of claim 9, wherein

the selector is configured to select the second operational voltage if the indication indicates that the settling time has expired.

12. The semiconductor device of claim 8, wherein

the read circuit is configured to apply one of a first current based on a first operational voltage and a second current based on a second operational voltage, the second current being less than the first current;

and

the selector is configured to select the second operational voltage if the read address does not match one of the stored write address; and

the selector is configured to select the second operational voltage if the indication indicates that the settling time has expired.

13. The semiconductor device of claim 12, wherein

the selector is configured to select the first operational voltage if the read address matches one of the stored write addresses and the indication indicates that the settling time has not expired.

14. The semiconductor device of claim 13, wherein

the first operational voltage changes with respect to temperature;

and

the second operational voltage does not change with respect to temperature.

15. The semiconductor device of claim 13, wherein the read circuit comprises:

a read bias unit configured to generate the first current based on the first operational voltage, configured to generate the second current based on the second operational voltage, and configured to output one of the first and second currents to the non-volatile memory cell array based on at least one control bias;

a current clamping circuit configured to restrict flow of current from the read bias unit to the non-volatile memory cell array; and

a bias selection unit configured to generate the control bias based on output from the selector.

16. The semiconductor device of claim 15, wherein

the selector includes:

a timer configured to measure a time period indicative of the settling time of the data being written into the non-volatile memory cell array; and

a bias selector configured to generate a selection signal based output of the timer and a comparison result indicating whether the read address matches one of the stored write addresses; and

wherein

the bias selection unit is configured to generate the control bias based on the selection signal.

17. The semiconductor device of claim 8, wherein the selector comprises:

a timer configured to measure a time period indicative of the settling time of the data being written into the non-volatile memory cell array; and

a bias selector configured to generate a selection signal based on output of the timer and whether the read address matches one of the stored write addresses, the selection signal indicating the selection of the operational voltage.

18. The semiconductor device of claim 13, wherein the read circuit comprises:

a read bias unit configured to generate a current;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a control bias; and

a bias selection unit configured to supply one of the first and second operational voltages as the control bias based on output from the selector.

19. The semiconductor device of claim 8, wherein the read circuit comprises:

a read bias unit configured to generate a current based on a first control bias;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a second control bias;

a first bias selection unit configured to generate the first control bias based on output from the selector; and

a second bias selection unit configured to generate the second control bias based on output from the selector.

20. The semiconductor device of claim 1, wherein the read unit is configured to apply a read current based on a period of time since data was written in the non-volatile memory cell array if a match between the read address and one of the stored write addresses exits and the indication indicates that the settling time has not expired.

21. The semiconductor device of claim 20, wherein the read unit is configured to apply a lower read current as the period of time since data was written in the non-volatile memory cell array increases.

22. The semiconductor device of claim 20, wherein the settling time is divided into a plurality of intervals, and the read unit is configured to apply a different read current during each interval if a match between the read address and one of the stored write addresses exits and the indication indicates that the settling time has not expired.

23. The semiconductor device of claim 22, wherein the read unit comprises:

a read circuit configured to apply the read current to the non-volatile memory cell array;

a voltage generator configured to supply a plurality operational voltages; and

a selector configured to measure the plurality of intervals, and select at least one of the operational voltages for use by the read circuit in applying the read current based on the measurements and whether the read address matches one of the stored write addresses.

24. The semiconductor device of claim 23, wherein the operational voltage selected if the read address matches one of the stored write addresses and the settling time has not expired varies with temperature.

25. The semiconductor device of claim 22, wherein the read circuit comprises:

a read bias unit configured to generate a plurality of currents based on the plurality of operational voltages, and output one of the plurality of currents based on control biases;

a current clamping circuit configured to restrict flow of current from the read bias unit to the non-volatile memory cell array; and

a bias selection unit configured to generate the control biases based on output from the selector.

26. The semiconductor device of claim 24, wherein the selector comprises:

a timer configured to measure each interval, and output a timing signal associated with each interval, each timing signal indicating whether an amount of time since writing data is in the associated time interval; and

a logic circuit configured to generate a plurality of selection signals based on the timing signals and whether the read address matches one of the stored write addresses.

27. The semiconductor device of claim 22, wherein the read circuit comprises:

a read bias unit configured to generate a current;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a control bias; and

a bias selection unit configured to supply one of the plurality of operational voltages as the control bias based on output from the selector.

28. The semiconductor device of claim 22, wherein the read circuit comprises:

a read bias unit configured to generate a current based on a first control bias;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a second control bias;

a first bias selection unit configured to generate the first control bias based on output from the selector and at least one of the operational voltages; and

a second bias selection unit configured to generate the second control bias based on output from the selector and at least one of the operational voltages.

29. The semiconductor device of claim 1, wherein the write address buffer is divided into a plurality of units, each unit including at least one storage location, and each unit configured to generating a composite signal indicating whether the read address matches one of the write addresses stored in the unit.

30. The semiconductor device of claim 29, wherein the read unit comprises:

a read circuit configured to apply the read current to the non-volatile memory cell array;

a voltage generator configured to supply a plurality operational voltages; and

a selector configured to select at least one of the operational voltages for use by the read circuit in applying the read current based on the composite signal output from each unit and at least one indication of settling time of the data being written into the non-volatile memory cell array.

31. The semiconductor device of claim 30, wherein the selector selects the operational voltage such that the read current applied by the read circuit is higher if any of the composite signals indicates a match and the indication indicates the settling time has not expired than if one of (1) the indication indicates the settling time has expired and (2) none of the composite signals indicates a match.

32. The semiconductor device of claim 30, wherein

the settling time is divided into a plurality of intervals;

the selector includes;

a plurality of timers, each of the plurality of timers associated with a different one of the plurality of units, each timer configured to measure each interval and output a timing signal associated with each interval, each timing signal indicating whether an amount of time since writing data is in the associated time interval;

a plurality of logic circuits, each logic unit associated with a different one of the plurality of units and the associated timer, each logic circuit configured to generate a plurality of selection signals based on the timing signals from the associated timer and whether the read address matches one of the stored write addresses in the associated unit; and

a composite logic circuit generating a plurality of composite selection signals based on the selection signals output from the plurality of logic circuits.

33. The semiconductor device of claim 32, wherein

the selection signals output from each logic circuit indicate the operational voltage to select;

and

the composite logic circuit generates the composite selection signals to select one of the operational voltages indicated by the plurality of logic circuits that results in the highest read current.

34. The semiconductor device of claim 33, wherein the read circuit comprises:

a read bias unit configured to generate a plurality of currents based on the plurality of operational voltages, and output one of the plurality of currents based on control biases;

a current clamping circuit configured to restrict flow of current from the read bias unit to the non-volatile memory cell array; and

a bias selection unit configured to generate the control biases based on output from the selector.

35. The semiconductor device of claim 33, wherein the read circuit comprises:

a read bias unit configured to generate a current;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a control bias; and

a bias selection unit configured to supply one of the plurality of operational voltages as the control bias based on output from the selector.

36. The semiconductor device of claim 33, wherein the read circuit comprises:

a read bias unit configured to generate a current based on a first control bias;

a current clamping circuit configured to restrict flow of the current from the read bias unit to the non-volatile memory cell array based on a second control bias;

a first bias selection unit configured to generate the first control bias based on output from the selector and at least one of the operational voltages; and

a second bias selection unit configured to generate the second control bias based on output from the selector and at least one of the operational voltages.

37. A semiconductor device, comprising:

a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell;

a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array; and

a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of an amount of time since data was written into the non-volatile memory cell array.

38. A card, comprising:

a memory, the memory including;

a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell;

a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array;

a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array; and

a control unit configured to control the memory.

39. A system, comprising:

a bus;

a semiconductor device connected to the bus, the semiconductor device including;

a non-volatile memory cell array, memory cells of the non-volatile memory cell array being resistance based, and each memory cell having a resistance that changes over time after data is written into the memory cell;

a write address buffer configured to store write addresses associated with data being written into the non-volatile memory cell array;

a read unit configured to perform a read operation to read data from the non-volatile memory cell array, the read unit configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array; and

an input/output device connected to the bus; and

a processor connected to the bus, the processor configured to communicate with the input/output device and the semiconductor device via the bus.

40. A method of reading data from a semiconductor device, comprising:

storing data being written into the non-volatile memory cell array in a write buffer;

storing write addresses associated with data being written into the non-volatile memory cell array; and

controlling a read current applied to the non-volatile memory cell array during a read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.