Multi-serial interface stacked-die memory architecture

• US 7,978,721 B2
• Filed: 10/30/2008
• Issued: 07/12/2011
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joe M., LaBerge, Paul A.
• Primary Examiner(s): Phan; M.
• Application Number:
  US12/261,942
• Publication Number:
  US 20100005238A1
• Time in Patent Office: 985 Days
• Field of Search: 370419-464, 365200-230, 365151-195, 711103-105, 711111-171
• US Class Current: 370/419
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/16 Memory access
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destination devices such as a processor and a switch. At the switch, one or more commands, addresses, or data corresponding to each stream can be transferred to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault. The destination MVC can perform write operations, read operations, and/or memory vault housekeeping operations independently from concurrent operations associated with other MVCs coupled to a corresponding plurality of memory vaults.

Claims

1. A memory system, comprising:

a plurality of memory vaults comprising a stacked plurality of tiled memory arrays, each memory vault comprising a stacked plurality of memory array die sections;

a plurality of memory vault controllers (MVCs), each MVC coupled to a corresponding one of the plurality of memory vaults in a one-to-one relationship to communicate with the corresponding memory vault independently from communications between others of the plurality of MVCs and memory vaults corresponding to the others of the plurality of MVCs;

a plurality of configurable serialized communication link interfaces (SCLIs) configured for concurrent operation to communicatively couple the plurality of MVCs to at least one of an originating device or a destination device;

a switch coupled to the plurality of SCLIs and to the plurality of MVCs to cross-connect a selected SCLI to a selected MVC; and

a packet decoder coupled to the switch to receive an outbound packet sent from the originating device across an outbound one of the plurality of SCLIs, to extract at least one of an outbound memory command, an outbound memory address, or an outbound memory data field from the outbound packet and to present a set of memory vault select signals to the switch; and

a packet encoder coupled to the switch to receive at least one of an inbound memory command, an inbound memory address, or inbound memory data from one of the plurality of MVCs and to encode the inbound memory address or the inbound memory data into an inbound packet for transmission across an inbound one of the plurality of SCLIs to the destination device.

2. The memory system of claim 1, wherein the stacked plurality of memory array die sections comprises a single tile from each of the stacked plurality of tiled memory arrays.

3. The memory system of claim 1, wherein the plurality of memory array die sections corresponding to each memory vault are interconnected using through-wafer interconnects (TWIs).

4. The memory system of claim 1, further comprising:

a control register coupled to the switch to accept configuration parameters from a configuration source and to configure the switch to operate according to a selectable mode.

5. The memory system of claim 4, wherein the selectable mode includes at least one of operating the plurality of memory vaults synchronously in response to at least one request or operating the plurality of memory vaults asynchronously in response to at least one request.

13. The memory system of claim 1, each MVC further comprising:

a memory vault repair logic (MVRL) component to perform at least one of defective memory array address remapping operations or defective through-wafer interconnect (TWI) repair operations associated with the corresponding memory vault.

6. A memory system, comprising:

a plurality of memory vaults comprising a stacked plurality of tiled memory arrays, each memory vault comprising a stacked plurality of memory array die sections;

a plurality of memory vault controllers (MVCs), each MVC coupled to a corresponding one of the plurality of memory vaults in a one-to-one relationship to communicate with the corresponding memory vault independently from communications between others of the plurality of MVCs and memory vaults corresponding to the others of the plurality of MVCs;

a plurality of configurable serialized communication link interfaces (SCLIs) configured for concurrent operation to communicatively couple the plurality of MVCs to at least one of an originating device or a destination device, an outbound one of the plurality of SCLIs further comprising;

a plurality of outbound differential pair serial paths (DPSPs) coupled to the originating device to transport an outbound packet containing at least one of command information, address information, or data across the outbound SCLI, each of the plurality of outbound DPSPs to transport a first data rate outbound sub-packet portion of the outbound packet at a first data rate;

a deserializer coupled to the plurality of outbound DPSPs to convert each first data rate outbound sub-packet portion of the outbound packet to a plurality of second data rate outbound sub-packets for transmission across a first plurality of outbound single-ended data paths (SEDPs) at a second data rate, the second data rate slower than the first data rate; and

a demultiplexer communicatively coupled to the deserializer to convert each of the plurality of second data rate outbound sub-packets to a plurality of third data rate outbound sub-packets for transmission across a second plurality of outbound SEDPs to a packet decoder at a third data rate, the third data rate slower than the second data rate.

7. A memory system, comprising:

a plurality of memory vaults comprising a stacked plurality of tiled memory arrays, each memory vault comprising a stacked plurality of memory array die sections;

a plurality of memory vault controllers (MVCs), each MVC coupled to a corresponding one of the plurality of memory vaults in a one-to-one relationship to communicate with the corresponding memory vault independently from communications between others of the plurality of MVCs and memory vaults corresponding to the others of the plurality of MVCs;

a plurality of configurable serialized communication link interfaces (SCLIs) configured for concurrent operation to communicatively couple the plurality of MVCs to at least one of an originating device or a destination device;

a packet encoder communicatively coupled to the switch to packetize at least one of command information, address information, or data received from an MVC associated with the selected memory vault for transmission across an inbound one of the plurality of SCLIs to the destination device, to segment a resulting inbound packet into a plurality of third data rate inbound sub-packets, and to send the third data rate inbound sub-packets across a first plurality of inbound single-ended data paths (SEDPs) at a third data rate;

a multiplexer communicatively coupled to the packet encoder to multiplex each of a plurality of subsets of the third data rate inbound sub-packets into a second data rate inbound sub-packet and to send the second data rate inbound sub-packets across a second plurality of inbound SEDPs at a second data rate faster than the third data rate; and

a serializer communicatively coupled to the multiplexer to aggregate each of a plurality of subsets of the second data rate inbound sub-packets into a first data rate inbound sub-packet and to send the first data rate inbound sub-packets to the destination device across a plurality of inbound differential pair serial paths (DPSPs) at a first data rate faster than the second data rate.

9. The memory system of claim 7, wherein the memory sequencer comprises a dynamic random access memory (DRAM) sequencer.

8. A memory system, comprising:

a plurality of memory vaults comprising a stacked plurality of tiled memory arrays, each memory vault comprising a stacked plurality of memory array die sections;

a plurality of memory vault controllers (MVCs), each MVC coupled to a corresponding one of the plurality of memory vaults in a one-to-one relationship to communicate with the corresponding memory vault independently from communications between others of the plurality of MVCs and memory vaults corresponding to the others of the plurality of MVCs;

a plurality of configurable serialized communication link interfaces (SCLIs) configured for concurrent operation to communicatively couple the plurality of MVCs to at least one of an originating device or a destination device each MVC further comprising;

a programmable vault control logic (PVCL) component to interface the MVC to the corresponding memory vault and to generate at least one of bank control signals or timing signals associated with the corresponding memory vault;

a memory sequencer coupled to the PVCL, the memory sequencer to perform at least one of command decode operations, memory address multiplexing operations, memory address demultiplexing operations, memory refresh operations, memory vault training operations, or memory vault prefetch operations associated with the corresponding memory vault;

a write buffer coupled to the PVCL to buffer data arriving at the MVC from the originating device; and

a read buffer coupled to the PVCL to buffer data arriving at the MVC from the corresponding memory vault.

10. The memory system of claim 8, wherein the PVCL is configured to interface the MVC to the corresponding memory vault and to generate the bank control signals or timing signals according to specifications associated with a memory vault of at least one of a selected configuration or a selected technology.

11. The memory system of claim 8, wherein the memory sequencer is configured to perform the command decode operations, memory address multiplexing operations, memory address demultiplexing operations, memory refresh operations, memory vault training operations, or memory vault prefetch operations according to specifications associated with a memory vault of at least one of a selected configuration or a selected technology.

12. The memory system of claim 8, further comprising:

an out-of-order request queue associated with each MVC, the out-of-order request queue to order at least one of read operations to a plurality of memory banks or write operations to the plurality of memory banks to avoid sequential operations to any single memory bank.

14. A method, comprising:

concurrently transferring a plurality of streams of commands, addresses, or data;

concurrently switching at least one of a command, an address, or data associated with each stream to a corresponding destination memory vault controller (MVC) associated with a corresponding memory vault;

performing at least one of data write operations to write the outbound data to the corresponding memory vault, data read operations to read data from the corresponding memory vault, or memory vault housekeeping operations associated with the corresponding memory vault, the data write operations, data read operations, or housekeeping operations to be performed independently from concurrent operations associated with others of a plurality of MVCs coupled to a corresponding plurality of memory vaults;

segmenting a packet into a plurality of first data rate sub-packet portions of the packet, the packet containing at least one memory subsystem command, at least one memory subsystem address, or data to be written to at least one memory subsystem location or to be read from at least one memory subsystem location;

sending each of the first data rate sub-packets at a first data rate;

segmenting each of the first data rate sub-packets into a plurality of second data rate sub-packets;

sending each of the second data rate sub-packets at a second data rate slower than the first data rate;

segmenting each of the second data rate sub-packet into a plurality of third data rate sub-packets; and

sending the third data rate sub-packets to a packet decoder at a third data rate slower than the second data rate.

15. The method of claim 14, further comprising:

receiving a set of sub-packets corresponding to a packet;

assembling the set of sub-packets into the packet;

extracting at least one of the outbound command, the outbound address, or the outbound data from the packet; and

presenting the outbound command, the outbound address, or the outbound data.

16. The method of claim 14, further comprising:

buffering at least one of the outbound command, the outbound address, or the outbound data; and

presenting the outbound command, the outbound address, or the outbound data for processing.

17. The method of claim 16, further comprising:

ordering at least one of read operations to a plurality of memory banks associated with the corresponding memory vault or write operations to the plurality of memory banks.

18. The method of claim 14, further comprising:

operating a synchronous subset of the corresponding plurality of memory vaults in response to a single request to decrease access latency by synchronously transferring a wide data word of a width that is a multiple of a single memory vault word length, the multiple corresponding to a number of memory vaults in the synchronous subset.

19. A method, comprising:

creating a plurality of inbound data streams from command, address, or data read from each of a plurality of memory vaults;

switching the plurality of inbound data streams to a corresponding plurality of serialized communication link interfaces (SCLIs);

concurrently transferring the plurality of inbound streams across the plurality of SCLIs to at least one destination device

accessing an inbound data word from a selected memory bank associated with the corresponding memory vault in response to a read command;

presenting the inbound data word;

switching the inbound data word to a packet encoder associated with a selected one of the plurality of SCLIs;

packetizing the inbound data word into an inbound packet;

segmenting the inbound packet into a plurality of third data rate inbound sub-packets; and

sending the plurality of third data rate inbound sub-packets to a multiplexer at a third data rate.

20. The method of claim 19, further comprising:

multiplexing each of a plurality of subsets of the third data rate inbound sub-packets into a second data rate inbound sub-packet,

sending the second data rate inbound sub-packets at a second data rate;

aggregating each of a plurality of subsets of the second data rate inbound sub-packets into a first data rate inbound sub-packet;

presenting the first data rate inbound sub-packets;

assembling the first data rate inbound sub-packets into the inbound packet; and

extracting the inbound data word from the inbound packet.

21. The method of claim 20, further comprising:

presenting the inbound data word to an operating system associated with the at least one destination device.