Powered device including a multi-use detection resistor

• US 7,979,168 B2
• Filed: 09/11/2008
• Issued: 07/12/2011
• Est. Priority Date: 07/25/2006
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Landry, D. Matthew, Velez, Alejandro
• Primary Examiner(s): Patel; Rajnikant B
• Application Number:
  US12/208,533
• Publication Number:
  US 20090001956A1
• Time in Patent Office: 1,034 Days
• Field of Search: 713300-330, 713/297, 324530-534, 323/280, 323282-284, 323/277, 700295-297
• US Class Current: 700/297
• CPC Class Codes: H04L 12/10 Current supply arrangements

Abstract

In a particular embodiment, a method includes receiving a powered device (PD) detection signal at a PD from a powered network and applying the PD detection signal to an external resistor to provide a detection signature to the powered network. Further, the method includes receiving a PD classification mark signal at the PD, applying the received PD classification mark signal to the external resistor, and selectively activating a classification mark current path in parallel with the external resistor to produce a classification mark signature.

Claims

1. A method comprising:

receiving a powered device (PD) detection signal at a PD from a powered network;

applying the PD detection signal to an external resistor to provide a detection signature to the powered network;

receiving a PD classification mark signal at the PD;

applying the received PD classification mark signal to the external resistor; and

selectively activating a classification mark current path in parallel with the external resistor to produce a classification mark signature.

2. The method of claim 1, wherein selectively activating a classification mark current path comprises:

activating a classification mark switch including a first terminal coupled to the external resistor and including a second terminal coupled to a classification mark current mirror;

wherein the classification mark current mirror is adapted to draw a second current that aggregates with a first current across the external resistor to produce the classification mark signature.

3. The method of claim 1, further comprising:

receiving a PD classification signal at the PD;

applying the PD classification signal to the external resistor; and

selectively activating a classification current path in parallel with the external resistor to produce a classification signature.

4. The method of claim 3, wherein selectively activating the classification current path comprises:

activating a classification switch including a first terminal coupled to the external resistor and a second terminal coupled to a classification current mirror;

wherein the classification current mirror is adapted to draw a third current that aggregates with a first current across the external resistor to produce a PD classification signature.

5. The method of claim 1, further comprising mirroring a current associated with the external resistor to produce a reference current for use by other components.

6. The method of claim 1, wherein the external resistor is coupled between a first pin responsive to a first voltage supply terminal and a second pin, wherein applying the detection voltage to the external resistor comprises:

activating a PD detection switch to couple the second pin to a second voltage supply terminal; and

isolating a classification mark current mirror from the second pin.

7. The method of claim 6, wherein selectively activating a classification mark current path comprises:

deactivating the PD detection switch to isolate the second pin from the second voltage supply terminal; and

activating a classification mark switch to couple the second pin to the second voltage supply terminal via the classification mark current path, wherein the classification mark current path places a current source in parallel with the external resistor.

8. A Power over Ethernet (PoE) powered device comprising:

an external resistor including a first terminal and a second terminal; and

an integrated circuit comprising;

a first pin coupled to the first terminal of the external resistor and coupled to a first power supply terminal;

a second pin coupled to the second terminal of the external resistor;

a first logic circuit to selectively couple the second pin to a second power supply terminal via a first current path in response to a powered device (PD) detection signal to produce a PD detection signature; and

a second logic circuit to selectively couple the second pin to the second power supply terminal via a second current path in response to a PD classification mark signal, the second current path including a current source in parallel with the external resistor to produce a PD classification mark signature.

9. The PoE powered device of claim 8, further comprising a third logic circuit to selectively couple the second pin to the second power supply terminal via a third current path in response to a PD classification signal, the third current path including a second current source in parallel with the external resistor to produce a PD classification signature.

10. The PoE powered device of claim 8, further comprising a fourth logic circuit to selectively couple at least one of the first and second pins to a reference voltage circuit to produce a reference current using the external resistor in response to receiving a power supply related to a PD classification related to the PD classification signal.

11. The PoE powered device of claim 8, wherein the PoE powered device further comprises an interface responsive to a powered network to receive power and data via a network cable.

12. The PoE powered device of claim 11, wherein the first logic circuit comprises:

a first switch coupled between the second pin and the second power supply terminal; and

a PD control circuit coupled to the interface and adapted to detect the PD detection signal, the PD control circuit to selectively activate the first switch in response to detecting the PD detection signal.

13. The PoE powered device of claim 12, wherein the second logic circuit comprises a second switch including a first terminal coupled to the second pin and to the current source, a control terminal coupled to the PD control circuit;

and a second terminal coupled to the second power supply terminal.

14. The PoE powered device of claim 12, wherein the PD classification mark signal comprises a voltage signal that is received after receiving at least one PD classification signal.

15. A circuit device comprising:

an interface coupled to a cable to receive power and data;

a first power supply terminal coupled to the interface;

a second power supply terminal coupled to the interface;

a first pin coupled to the first power supply terminal and to a first terminal of an external resistor;

a second pin coupled to a second terminal of the external resistor;

logic circuitry coupled to the interface and adapted to;

detect a first signal at the interface;

selectively couple the second pin to the second power supply terminal via a first current path in response to detecting the first signal to produce a first current;

detect a second signal at the interface; and

selectively couple the second pin to the second power supply terminal via a second current path that places a first current source in parallel with the external resistor in response to detecting the second signal to produce a second current.

16. The circuit device of claim 15, wherein the first current source includes a current mirror circuit comprising:

a first transistor including a first terminal coupled to the second pin, a first control terminal coupled to the first terminal, and a second terminal coupled to the second power supply terminal; and

a second transistor including a third terminal coupled to the first power supply terminal, a second control terminal coupled to the first control terminal, and a fourth terminal coupled to the second power supply terminal.

17. The circuit device of claim 16, wherein the current mirror circuit further includes at least one second transistor pair coupled in series with the first and second transistors to produce the second current.

18. The circuit device of claim 16, wherein the second transistor has a second width that is greater than a first width of the first transistor.

19. The circuit device of claim 16, wherein the second transistor is adapted to generate a second current that is larger than a first current associated with the first transistor.

20. The circuit device of claim 15, wherein, before receiving the second signal, the logic circuitry is further adapted to:

detect a third signal at the interface; and

selectively couple the second pin to the second power supply terminal via a third current path that places a second current source in parallel with the external resistor in response to detecting the third signal to produce a third current.

21. The powered device of claim 15, wherein, after producing the second current, the logic circuitry is adapted to selectively couple the first pin to a reference voltage source to produce a reference current.