Configurable voltage regulator

• US 7,979,224 B2
• Filed: 08/25/2010
• Issued: 07/12/2011
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutardja, Sehat
• Primary Examiner(s): Tsai; Carol S
• Application Number:
  US12/862,815
• Publication Number:
  US 20100321037A1
• Time in Patent Office: 321 Days
• Field of Search: 702/105, 702/85, 702/65, 702/121, 702/106, 324/73.1, 324/537, 324/534, 324/649, 324/500, 324/509, 324/642, 361/149, 361/194, 361/189.9, 326/30
• US Class Current: 702/65
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03F 2200/261 Amplifier which being suitable for instrumentation applications
• CPC Class Codes: H03F 2203/45138 Two or more differential amplifiers in IC-block form are combined, e.g. measuring amplifiers
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03H 11/1291 Current or voltage controlled filters
• CPC Class Codes: H03H 11/30 Automatic matching of source impedance to load impedance
• CPC Class Codes: H03H 7/0153 Electrical filters; Controlling thereof
• CPC Class Codes: H03H 7/40 Automatic matching of load impedance to source impedance

Abstract

A configurable semiconductor device includes at least one select pin configured to connect to one of a plurality of impedances. The impedances are external to the configurable semiconductor device and have impedance values within predetermined tolerances. A measurement circuit is connected to the at least one select pin. The measurement circuit is configured to measure electrical characteristics of the plurality of impedances, correlate the electrical characteristics to respective predetermined ranges of impedances, and generate digital output values corresponding to the correlation. A controller is configured to control a characteristic of the configurable semiconductor device based on the digital output values. Spacing between the respective predetermined ranges of impedances is based on the predetermined tolerances.

Claims

1. A configurable semiconductor device, comprising:

at least one select pin configured to connect to one of a plurality of impedances, wherein the impedances are external to the configurable semiconductor device and have impedance values within predetermined tolerances;

a measurement circuit connected to the at least one select pin, the measurement circuit configured to i) measure electrical characteristics of the plurality of impedances, ii) correlate the electrical characteristics to respective predetermined ranges of impedances, and iii) generate digital output values corresponding to the correlation; and

a controller configured to control a characteristic of the configurable semiconductor device based on the digital output values,

wherein spacing between the respective predetermined ranges of impedances is based on the predetermined tolerances.

2. The configurable semiconductor device of claim 1, wherein one of the respective predetermined ranges is defined by an upper range value that corresponds to an upper tolerance value of the impedance values.

3. The configurable semiconductor device of claim 1, wherein one of the respective predetermined ranges is defined by a lower range value that corresponds to a lower tolerance value of the impedance values.

4. The configurable semiconductor device of claim 1, wherein an upper range value of a first one of the respective predetermined ranges is less than or equal to a lower range value of a second one of the respective predetermined ranges that is adjacent to the first one of the respective predetermined ranges.

5. The configurable semiconductor device of claim 1, further comprising a storage circuit configured to i) store variable values for controlling the characteristic and ii) select the variable values based on the digital output values.

6. The configurable semiconductor device of claim 1, further comprising an address generator configured to determine memory locations corresponding to the digital output values.

7. The configurable semiconductor device of claim 1, wherein each of the respective predetermined ranges of impedances corresponds to a different one of the digital output values.

8. The configurable semiconductor device of claim 1, wherein each of the impedance values is selected to be centered within one of the respective predetermined ranges.

9. A method of operating a configurable semiconductor device, the method comprising:

connecting at least one select pin of the configurable semiconductor device to one of a plurality of impedances, wherein the impedances are external to the configurable semiconductor device and have impedance values within predetermined tolerances;

measuring electrical characteristics of the plurality of impedances;

correlating the electrical characteristics to respective predetermined ranges of impedances;

generating digital output values corresponding to the correlation; and

controlling a characteristic of the configurable semiconductor device based on the digital output values,

wherein spacing between the respective predetermined ranges of impedances is based on the predetermined tolerances.

10. The method of claim 9, wherein one of the respective predetermined ranges is defined by an upper range value that corresponds to an upper tolerance value of the impedance values.

11. The method of claim 9, wherein one of the respective predetermined ranges is defined by a lower range value that corresponds to a lower tolerance value of the impedance values.

12. The method of claim 9, wherein an upper range value of a first one of the respective predetermined ranges is less than or equal to a lower range value of a second one of the respective predetermined ranges that is adjacent to the first one of the respective predetermined ranges.

13. The method of claim 9, further comprising:

storing variable values for controlling the characteristic; and

selecting the variable values based on the digital output values.

14. The method of claim 9, further comprising determining memory locations corresponding to the digital output values.

15. The method of claim 9, wherein each of the respective predetermined ranges of impedances corresponds to a different one of the digital output values.

16. The method of claim 9, further comprising selecting each of the impedance values to be centered within one of the respective predetermined ranges.